Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-06-20
2006-06-20
Ton, David (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000
Reexamination Certificate
active
07065691
ABSTRACT:
A computer system has at least one processor, a memory system, a Joint Test Action Group (JTAG) bus interface, and Input/Ouput devices. At least one Input/Ouput device of the system has an integrated circuit connected to and readable by the JTAG bus interface. The memory system of the computer system contains an exception handler capable of reading a state of the readable integrated circuit of the Input/Output device upon occurrence of an exception.
REFERENCES:
patent: 5875294 (1999-02-01), Roth et al.
patent: 5909574 (1999-06-01), Meyer
patent: 6094729 (2000-07-01), Mann
patent: 6185523 (2001-02-01), Itskin et al.
patent: 6446221 (2002-09-01), Jaggar et al.
patent: 6829701 (2004-12-01), Roth et al.
patent: 6886111 (2005-04-01), Tran
patent: 6898731 (2005-05-01), Hack et al.
Erickson Michael John
Mantey Paul John
Hewlett--Packard Development Company, L.P.
Ton David
LandOfFree
Apparatus and method for saving precise system state... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for saving precise system state..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for saving precise system state... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3691543