Apparatus and method for performing bit de-collection in a...

Details Apparatus and method for performing bit de-collection in a... Apparatus and method for performing bit de-collection in a...

2007-09-11

2007-09-11

Lamarre, Guy (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S702000, C714S768000, C714S786000

Reexamination Certificate

active

10989557

ABSTRACT:
An apparatus and a method for performing a bit de-collection according to a hybrid automatic retransmission request are disclosed. The apparatus includes a column counter for increasing one column every four bits and outputting a position of a current column in response to received bit sequences; a state detector for outputting state information of the current column by means of an output value of the column counter, a parameter denoting a number of rows to which systematic bits have been assigned, and a parameter denoting a number of columns to which the systematic bits have been assigned; and address generators for generating write addresses required for performing a write operation and read addresses required for performing a read operation according to the state information output from the state detector.

REFERENCES:
patent: 6744744 (2004-06-01), Tong et al.
patent: 6854077 (2005-02-01), Chen et al.

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