Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2008-01-15
2008-01-15
Lamarre, Guy (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S718000, C714S733000
Reexamination Certificate
active
07320100
ABSTRACT:
A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
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Bethard Roger A.
Dixon R. Paul
Grossmeier Alan M.
Higgins Michael F.
Marquardt Kelly J.
Cray Inc.
Lamarre Guy
Lemaire Charles A.
Lemaire Patent Law Firm, P.L.L.C.
Rizk Sam
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