Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-09-12
2001-10-09
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S210130
Reexamination Certificate
active
06301165
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an apparatus and a method for detecting faulty cells in a semiconductor memory device.
2. Description of the Related Art
Due to the development of very large scale integration (VLSI) technology, the integration density and the operating speed of chips is increasing. Also, in order to reduce the area of chips, a narrow line width technology has been adopted. As a result, more cells can be integrated in the same chip area. Techniques for testing whether faults exist in chips have been a matter of concern as VLSI technology has developed.
Various causes of faults in a VLSI circuit can be simply modeled. Among fault models of VLSI circuits, the most common one is a stuck-at fault model. Using the stuck-at fault model, it is possible to detect a logic operation fault, where the logic level of a node in the circuit is “stuck at” a logic “0” or “1”. However, it is difficult to detect a parametric fault or a transient fault, which prohibit the normal operation of chips by affecting delay time, using the stuck-at fault model. Therefore, a current test is used in order to detect these faults.
It is possible to detect whether faults exist in the circuit by the current test using a phenomenon in which excessive current is generated in the circuit due to the parametric fault or the transient fault. The current test can be classified as an on-chip test or an off-chip test, depending upon whether a current detector for detecting current in the circuit is loaded into the chip. In the on-chip test, it is determined by the built-in current detector whether the chip is faulty. In the off-chip test, it is determined whether the chip is faulty using a current detector included in external test equipment.
However, in the case of the off-chip test performed using the test equipment, current generated in the tested chip is transmitted to the test equipment through the output pin of the tested chip. Accordingly, current resolution may deteriorate. Also, when the operating speed of the test equipment is lower than the operating speed of the tested chip, current detection speed decreases. Accordingly it takes longer to test the chip.
The on-chip test is mainly used for a test for detecting faulty cells in a semiconductor memory device. In the case of the on-chip test, since the current detector is integrated into the tested chip, current is analyzed in the tested chip and the analysis result is output. Therefore, the degree of correctness in detecting faults increases. Also, since the test speed of the on-chip test corresponds to the operating speed of the tested chip, the test speed significantly increases. However, in the on-chip test, the layout area of the tested chip increases and the normal operating speed of the chip may decrease, due to the integrated current detector.
Therefore, a minimum number of current detectors must be used when the circuit is designed for performing the on-chip test. According to the conventional circuit for detecting faulty cells in the semiconductor memory device, the number of current detectors is restricted. As a result, although it is possible to detect whether faulty cells exist, it is difficult to detect the correct positions of the faulty cells.
SUMMARY OF THE INVENTION
To solve the above problem, it is an object of the present invention to provide an apparatus and method for detecting faulty cells in a semiconductor memory device, using a minimum number of built-in current detectors, the apparatus being capable of correctly detecting whether faulty memory cells exist and where the faulty memory cells are located, and for minimizing the decrease in the operating speed of a tested chip due to the built-in current detectors during a normal operation.
In accordance with the invention, there is provided an apparatus for detecting faulty cells in a semiconductor memory device. The apparatus includes a memory cell array comprising a plurality of memory blocks, each of which comprises a plurality of memory cells which are addressable by predetermined corresponding memory addresses. A plurality of faulty cell detectors correspond to the plurality of memory blocks. The plurality of faulty cell detectors compare currents generated in the memory blocks to a predetermined reference current and detect whether addressed memory cells are faulty.
In one embodiment, the outputs of the plurality of faulty cell detectors are provided through data input and output lines in response to a test selection signal.
In one embodiment, each of the faulty cell detectors includes a current detector for detecting current flowing through the memory block according to the memory address. The current detector compares the magnitude of the detected current with the magnitude of the reference current and provides the result of the comparison as an output. In this embodiment, a selector receives data read from the bitline of the addressed memory cell according to the memory address. The selector receives the comparison result from the current detector and provides one of the read data and the comparison result of the current detector as an output in response to the test selection signal. In one particular embodiment, each of the faulty cell detectors also includes a switch for bypassing the current detectors corresponding to the memory blocks in response to the test selection signal.
In another aspect, the invention is directed to a method of detecting faulty cells in a semiconductor memory device which includes memory cell arrays, each of which includes a plurality of memory blocks, each of which includes a plurality of memory cells addressable by predetermined corresponding memory addresses. In accordance with the method, the memory device is set to be in a test mode, and the memory addresses are applied to the memory device. Currents flowing through the plurality of memory blocks are detected by memory cells addressed according to the memory addresses. It is determined whether the detected currents are larger than reference current. A memory cell in a memory block addressed by a memory address is determined to be faulty if the detected current is determined to be larger than the reference current. A memory cell in a memory block addressed by a memory address is determined to be a normal cell if the detected current is determined to be less than or equal to the reference current.
In one embodiment, the result of the determination as to whether a cell is faulty or normal is provided as an output through data input and output lines of the memory device.
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patent: 5606527 (1997-02-01), Kwack et al.
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patent: 6058056 (2000-05-01), Beffa et al.
patent: 6085334 (2000-07-01), Giles et al.
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Dinh Son T.
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
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