Apparatus and method for bit pattern learning and computer...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S785000

Reexamination Certificate

active

11093244

ABSTRACT:
A computer calculates bit patterns of syndromes for all candidate bit patterns of reception words that are input in ECC-EOR circuits of a logic circuit. The bit patterns of the syndromes are stored as possible bit patterns. Request bit patterns are propagated when an error occurs, and are allocated to the syndromes. Implication processing is performed, and the request bit patterns are compared with the possible bit patterns.

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patent: 6130625 (2000-10-01), Harvey
patent: 6275799 (2001-08-01), Iso
patent: 5-5774 (1993-01-01), None

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