Apparatus and method for adapting a level sensitive device...

Details Apparatus and method for adapting a level sensitive device... Apparatus and method for adapting a level sensitive device...

2006-04-18

2006-04-18

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000

Reexamination Certificate

active

07032149

ABSTRACT:
A circuit for adapting a level sensitive memory device to exhibit edge-triggered behavior. The adapter circuit can be used with testing modules that expect edge-triggered behavior. The adapting circuit may include address decoding circuitry and output storage and delay circuitry.

REFERENCES:
patent: 5463338 (1995-10-01), Yurash
patent: 5504441 (1996-04-01), Sigal
patent: 5831868 (1998-11-01), Beausang et al.
patent: 6529033 (2003-03-01), Park et al.
patent: 6564347 (2003-05-01), Mates

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