Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-05-10
2002-04-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000
Reexamination Certificate
active
06372587
ABSTRACT:
BACKGROUND OF THE INVENTION
1. FIELD OF THE INVENTION
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of forming a halo implant in a substrate adjacent one side of a structure such as a gate structure of a transistor.
2. DESCRIPTION OF THE RELATED ART
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the channel length of a transistor also increases “short-channel” effects, almost by definition. Short-channel effects include, among other things, an increased drain-source leakage current when the transistor is supposed to be switched “off,” due to source/drain depletion regions being closer together because of the shorter channel length. Short-channel effects also include “threshold roll-off” (i.e., the threshold voltage V
th
decreasing as gate length is reduced), and the like.
Short-channel effects may be reduced by using angled halo implants. Angled halo implants are implants of dopants that effectively “reinforce” the doping type of the substrate in the channel between the source/drain extension (SDE) regions (formerly known as lightly doped drain or LDD regions). For example, for an N-MOS transistor, the doping type of the substrate in the channel between the n-type source/drain extension (SDE) regions is p-type. The angled halo implant may be boron (B) or boron difluoride (BF
2
) implanted into the substrate at an angle (with respect to a direction perpendicular to the surface of the substrate), and with a dose that may range from about 1.0×10
12
-1.0×10
14
ions/cm
2
at an implant energy ranging from about 5-15 keV for B and about 20-70 keV for BF
2
.
Similarly, for a P-MOS transistor, the doping type of the substrate in the channel between the p-type source/drain extension (SDE) regions is n-type. The angled halo implant may be arsenic (As) implanted into the substrate at an angle (with respect to a direction perpendicular to the surface of the substrate), and with a dose that may range from about 1.0×10
12
-1.0×10
14
ions/cm
2
at an implant energy ranging from about 40-70 keV for As.
As shown in
FIG. 1
, for example, a metal oxide semiconductor field effect transistor (MOSFET or MOS transistor)
100
may be formed on a semiconducting substrate
105
, such as doped-silicon. The MOS transistor
100
may have a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate
110
formed above a gate oxide
115
formed above the semiconducting substrate
105
. The doped-poly gate
110
and the gate oxide
115
may be separated from N
+
-doped (P
+
-doped) source/drain regions
120
of the MOS transistor
100
by dielectric spacers
125
. The dielectric spacers
125
may be formed above shallow N-doped (P-doped) source/drain extension (SDE) regions
130
.
As shown in
FIG. 1
, P
−
-doped (N
−
-doped) angled halo implants
135
are typically provided adjacent the N-doped (P-doped) SDE regions
130
to reduce some of the short-channel effects described above. In particular, by “reinforcing” the p-doping (n-doping) type of the semiconducting substrate
105
in the channel between the N-doped (P-doped) SDE regions
130
, the laterally non-uniform P
−
-doped (N
−
-doped) angled halo implants
135
may be better at controlling the threshold roll-off (i.e., the threshold voltage V
th
decreasing as gate length is reduced), thereby reducing short-channel induced effects such as a non-zero drain-source leakage current when the transistor is supposed to be switched “off,” (i.e., “off-state” leakage). As shown in
FIG. 1
, shallow trench isolation (STI) regions
140
may be provided to isolate the MOS transistor
100
electrically from neighboring semiconductor devices such as other MOS transistors (not shown).
As shown in
FIG. 2
, only one P
−
-doped (N
−
-doped) angled halo implant
235
typically needs to be provided adjacent the N-doped (P-doped) SDE region
230
adjacent the N
+
-doped (P
+
-doped) source region
220
of the MOS transistor
200
to reduce some of the short-channel effects described above. Note that elements of the MOS transistor
200
that are substantially identical to the elements of the MOS transistor
100
as shown in
FIG. 1
are numbered identically.
As shown in
FIG. 3
, a conventional technique for implanting the asymmetric P
−
-doped (N
−
-doped) angled halo implant
235
is schematically illustrated. A structure
300
(that will eventually become a gate structure for an MOS transistor such as the MOS transistor
200
, as described above), having a doped-poly gate
110
and a gate dielectric
115
, may be masked by a mask
310
. The mask
310
may be formed of photoresist, for example, and may have a thickness in a range of about 5000 Å15000 Å.
As shown in
FIG. 3
, a halo dopant
320
(indicated by directed lines) may be implanted to introduce dopant atoms and/or molecules to form the asymmetric P
−
-doped (N
−
-doped) angled halo implant
235
only under the lefthand side of the structure
300
. As shown in
FIG. 3
, an angle &thgr; of the halo dopant
320
with respect to an upper surface
145
of the semiconducting substrate
105
may lie within a range of about 25°-65°.
Typically, the semiconducting substrate
105
is tilted at the angle &thgr; with respect to a horizontal direction in an implanter (not shown) and the halo dopant
320
is directed downward in a vertical direction. Alternatively, the semiconducting substrate
105
could be disposed in the horizontal direction in the implanter (not shown) and the halo dopant
320
could be directed downward at the angle &thgr; with respect to the horizontal direction in the implanter, and/or any other combination of tilt and implant direction could be used as long as the angle &thgr; is the relative angle of the halo dopant
320
with respect to the upper surface
145
of the semiconducting substrate
105
.
After implanting one side of the structure
300
, the semiconducting substrate
105
is typically rotated through 180° and the halo dopant
320
is again implanted so that the angle &thgr; is the relative angle of the halo dopant
320
with respect to the upper surface
145
of the semiconducting substrate
105
. If the mask
310
were not present, such symmetrical implanting of both sides of the structure
300
would result in symmetrical angled halo implants similar to the angled halo implants
135
shown in FIG.
1
. With the mask
310
present, however, symmetrical implanting of both sides of the structure
300
results in an asymmetrical angled halo implant similar to the asymmetrical angled halo implant
235
shown in
FIGS. 2 and 3
.
The halo dopant
320
may also be implanted into a region
330
(outlined in phantom) that will eventually become the N-doped (P-doped) SDE region
230
, and into a r
Cheek Jon D.
Luning Scott D.
Wristers Derick J.
Advanced Micro Devices , Inc.
Le Dung A
Williams Morgan & Amerson
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