Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – With textured surface
Reexamination Certificate
1998-08-07
2002-04-02
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
With textured surface
C257S753000, C257S759000
Reexamination Certificate
active
06365968
ABSTRACT:
BACKGROUND OF THE INVENTION
As device speeds increase, parasitic capacitance increasingly becomes a design factor. This is especially true more recently in semiconductor electro-optical devices. As the optical qualities continue to be incrementally refined, parasitic capacitances in these already small devices become the criticality in the speed of operation.
In electro-optical devices, the metal contact layers and wire bond pads give rise to a large proportion of total device capacitance. For example, considering the example of ridge-waveguide architectures, ridge structures function as waveguides in optically-active epitaxial layers (epilayers) to produce lasers and modulators, or even passive waveguides. In most configurations, the ridge is etched into the epilayers, and a wire bond pad is constructed adjacent to the ridge. A p-metal contact layer, below the pad, conducts current between the pad and the top of the ridge structure so that current is injected down through the ridge and the underlying active layer to the substrate. Current is controlled to be injected only through the ridge by a passivation/insulation layer that is located between the semiconductor and metal contact layer in all places but the ridge top. The current is injected to create light generation at the active layer in the case of a laser. It also can apply the reverse bias voltage to control the absorption properties in the case of a modulator. Other cases include an optical switch, optical detector, optical amplifier, or integrated waveguide device in which at least two of the mentioned devices are integrated. In these devices, the largest structures are the bond pads adjacent to the ridge, which are capacitively coupled to the typically grounded substrate of the device.
In the past, silicon oxide, i.e., silicon dioxide, has been used under the metal contact layer and bond pad as the passivation layer and to facilitate planarization, if necessary. There are certain advantages associated with this material system. Silicon oxide deposition processes are well-known and integrated into existing fabrication lines, and it further adheres well to gallium arsenide- and silicon-based substrates. Moreover, good adhesion can be obtained between the metal contact layers and the silicon oxide, reducing the risk of wire pull-off after wire bonding processes to the wire bond pad.
Silicon oxide, however, has drawbacks that are related to the device's electrical properties. Silicon oxide's dielectric properties create intrinsic limitations. Moreover, capacitance is proportional to the size of conductors and inversely proportional to the distance between conductors. Assuming that the size of the bond pad can not be made smaller due to the mechanics of wire bonding to the pad, the only way to decrease capacitance is to increase the distance between the contact layer and substrate, but stress-free silicon oxide layers of a micron or thicker are difficult to produce. Thus, a different material system is needed to further reduce capacitance.
Accordingly, some have replaced silicon oxide with polyimide passivation layers. Polyimide has considerably more favorable dielectric properties, can be similarly integrated into the existing device fabrication production lines, and has well characterized performance in electronic devices through its ubiquitous use in electronic circuit boards. This has occurred because of polyimide's attractive balance of thermal, mechanical, and electrical properties.
SUMMARY OF THE INVENTION
Experimentation has exposed a problem associated with the use of polyimide as an insulation layer. Poor adhesion at the polyimide layer in semiconductor systems can raise performance issues in commercial-grade devices.
Adhesion of the polyimide to the semiconductor layer, such as a silicon oxide coverage layer, can be controlled. Recent developments in adhesion promoters facilitate the chemical preparation of silicon oxide passivation layers, for example, to receive the polyimide.
The problems instead arise when the metal contact layers are deposited on the polyimide. Good adhesion is required because wire bonding processes, such as ultrasonic wire bonding, create substantial mechanical stress at the polyimide/contact layer junction. This can cause substantial failures at the time of wire bonding or later during deployment at the junction. In most cases, such uncertainties are unacceptable in a commercial device.
The present invention is directed to an electro-optical device and method for its fabrication. The invention utilizes a polymeric dielectric layer, which preferably polyimide. Consequently, capacitance is minimized because of polyimides favorable dielectric properties and the thickness to which it can be deposited to facilitate the high speed operation of the device. According to the invention, however, a silicon oxide interlayer is used between the metal contact layer and the polyimide. This bi-layer of silicon oxide and polyimide facilitates the ultimate adhesion between the metal contact layer and the underlying device since good adhesion can be obtained between the silicon oxide layer and the polyimide layer with the invention and between the metal layer and silicon oxide layer.
Preferably, the polyimide is roughened to increase the surface area contact between the polyimide layer and silicon oxide layer to further increase adhesion and thus the pull-off force required to separate the metal contact layer from the device. While such roughening can be achieved through plasma etching, in a preferred embodiment, the polyimide layer is roughened by patterned etching. Specifically, a patterned photoresist is used as a etch-protection layer to form a series of wells in the polyimide layer. Preferably, the pitch between successive wells is 1 to 20 microns.
This approach is also useful in reverse-ridge configurations where, with conventional processes, it is additionally difficult to obtain good silicon oxide coverage underneath the ridge overhang and thus planarization.
The above and other features of the invention including various novel details of construction and combinations of parts, and other advantages, will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular method and device embodying the invention are shown by way of illustration and not as a limitation of the invention. The principles and features of this invention may be employed in various and numerous embodiments without departing from the scope of the invention.
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Lu Hanh
Qian Yi
Sahara Richard
Corning Lasertron, Inc.
Hamilton Brook Smith & Reynolds P.C.
Jackson, Jr. Jerome
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