Amorphous silicon disposable spacer to reduce mask count in...

Details Amorphous silicon disposable spacer to reduce mask count in... Amorphous silicon disposable spacer to reduce mask count in...

1999-03-26

2001-04-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S304000, C438S305000, C438S306000, C438S307000

Reexamination Certificate

active

06214655

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device on a semiconductor substrate. The invention has particular applicability in manufacturing a plurality of semiconductor devices of different conductivity types on a single substrate.
BACKGROUND ART
Metal oxide semiconductor (MOS) devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate, a channel region separating the source/drain regions, and a thin gate oxide and a conductive gate comprising polysilicon or other conductive material formed above the channel region. In a typical integrated circuit, a plurality of MOS devices of different conductivity types, such as n-type and p-type, are formed on a common substrate.
A traditional approach to forming MOS devices of different conductivity types on a single substrate is illustrated in
FIGS. 1A-1G
. As shown in
FIG. 1A
, field oxide areas
115
are formed, as by local oxidation of silicon (LOCOS) or shallow trench isolation (STI), in semiconductor substrate
100
, then a thin gate oxide
105
is thermally grown, and conductive gates
110
, such as polysilicon, are formed. A photoresist mask M
1
is thereafter formed on the areas to be subsequently implanted with p-type impurities, and substrate
100
is implanted, as by ion implantation, with n-type impurities NLDD to form lightly or moderately doped regions
120
, also called “shallow source/drain extensions” (see FIG.
1
B). Adverting to
FIG. 1C
, mask M
1
is then removed, and the areas previously implanted with impurities NLDD are masked with photoresist mask M
2
. Substrate
100
is thereafter implanted, as by ion implantation, with p-type impurities PLDD to form lightly or moderately doped regions
125
.
Next, as shown in
FIG. 1D
, sidewall spacers
130
are formed on the side surfaces of the gates
110
, as by depositing a blanket layer of a dielectric material, such as silicon nitride, and anisotropically etching. A photoresist mask M
3
is thereafter formed on the regions implanted with p-type impurities (see FIG.
1
E), and substrate
100
is implanted, as by ion implantation, with n-type impurities NS/D to form source/drain regions
135
, which include lightly or moderately doped regions
120
. Adverting to
FIG. 1F
, mask M
3
is then removed, and the areas previously implanted with impurities NS/D are masked with photoresist mask M
4
. Substrate
100
is thereafter implanted, as by ion implantation, with p-type impurities PS/D to form source/drain regions
140
. Mask M
4
is then removed, leaving the structure shown in FIG.
1
G.
Source/drain implants NS/D, PS/D are typically implanted at a higher energy and dosage than lightly or moderately doped implants NLDD, PLDD, so source/drain implants NS/D, PS/D penetrate deeper into substrate
100
than lightly or moderately doped implants NLDD, PLDD. Additionally, sidewall spacers
130
prevent heavy source/drain implants NS/D, PS/D from entering substrate
100
adjacent to or under gates
110
to obtain the desired device performance characteristics. Thus, source/drain regions
135
,
140
have a step corresponding to spacer
130
.
Disadvantageously, the above-described methodology employs four photoresist masks (M
1
-M
4
), each of which requires the steps of spinning on the photoresist, exposing it with a stepper, developing the photoresist, and stripping off the mask after ion implantation. Each of these steps adds to the cost of the semiconductor device and decreases manufacturing throughput, and also subjects the device to additional handling, thereby increasing the likelihood of defects.
Moreover, masks M
1
-M
4
are all “critical masks”; i.e., extremely complex and difficult to design and use. The large number of fine features required to form the masks challenge the capabilities of the photolithographic process necessary to implement them, thereby increasing manufacturing costs and reducing production throughput. As design rules are reduced to 0.18 &mgr;m and under, e.g., 0.15 &mgr;m and under, to meet increasing demands for miniaturization and higher circuit density, shrinking feature sizes cause masks such as M
1
-M
4
to become even more difficult and costly to design and use.
Accordingly, there exists a need for a method of manufacturing MOS semiconductor devices with a reduced number of critical masks, thereby reducing manufacturing costs and increasing production throughput.
SUMMARY OF THE INVENTION
An advantage of the present invention is a method of forming a plurality of MOS devices of different conductivity types on a common substrate using a minimal number of critical masks, thereby reducing manufacturing costs and increasing production throughput.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises forming first and second conductive gates on a main surface of a semiconductor substrate with a gate dielectric layer therebetween; forming amorphous silicon sidewall spacers on side surfaces of the gates and extending onto the main surface; forming a first mask on the first gate and extending onto a first portion of the main surface; ion implanting impurities, using the second gate and sidewall spacers thereon as a mask, to form first moderate or heavy source/drain implants; removing the amorphous silicon sidewall spacers from the side surfaces of the second gate; ion implanting impurities, using the second gate as a mask, to form first lightly or moderately doped source/drain extension implants; removing the first mask; forming a second mask on the second gate and extending onto a second portion of the main surface; ion implanting impurities, using the first gate and sidewall spacers thereon as a mask, to form moderate or heavy second source/drain implants; removing the amorphous silicon sidewall spacers from the side surfaces of the first gate; and ion implanting impurities, using the first gate as a mask, to form second lightly or moderately doped source/drain extension implants.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.


REFERENCES:
patent: 5610088 (1997-03-01), Chang et al.
patent: 5736466 (1998-04-01), Wu
patent: 5804499 (1998-09-01), Dehm et al.
patent: 5946581 (1999-08-01), Garding et al.
K. Noda et al., “A 2.9 &mgr;m2Embedded SRAM Cell with Co-Salicide Direct-Strap Technology for 0.18 &mgr;m High Performance CMOS Logic”,IEDM Technical Digest, Dec., 1997, pp. 847-850.

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