Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-15
2001-12-18
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S964000
Reexamination Certificate
active
06331465
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to an alternate method and structure for improved floating gate tunneling devices.
BACKGROUND OF THE INVENTION
Modern integrated circuit technology relies on transistors to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever increasing number of linked transistors. As the number of transistors required increases, the surface area that can be dedicated to a single transistor dwindles. Today, also, low voltages are desired for low power, portable, battery operated circuits and systems. Thus, it is desirable to construct integrated circuit components which can operate at low voltage levels and accommodate higher density arrangement on the surface of the silicon chip.
Non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, offer the prospect of very high density structures. Flash memories are one form of FLOTOX devices and electronically erasable and programmable read only memories (EEPROMs) are another. Due to their high density nature, memories formed with FLOTOX transistors have the potential of replacing hard storage disk drives in computer systems. The advantages to this substitution would be in replacing a complex and delicate mechanical system with a rugged and easily portable small solid-state non-volatile memory system. There is also the possibility that given more speed of operation, particularly in the erase operation, that FLOTOX transistors might be used to replace dynamic random access memories (DRAMs). Thus, FLOTOX transistors might eventually have the ability to fill all memory needs in future computer systems.
In operation, FLOTOX transistors can be electronically programmed, erased, and reprogrammed. In FLOTOX transistors a floating gate is electrically isolated and any charge stored on the floating gate is trapped. Storing sufficient charge on the floating gate will create an inversion channel between source and drain of the transistor. Thus, the presence or absence of charge on the floating gate represents two distinct data states.
Typically, FLOTOX transistors are selectively programmed, or “written to,” by hot electron injection which places a charge on a floating gate during a write. The FLOTOX transistors are selectively erased by Fowler-Nordheim tunneling which removes the a charge from the floating gate. During a write, a high programming voltage is placed on a control gate. This forces an inversion region to form in the p-type substrate. The drain voltage is increased to approximately half the control gate voltage while the source is grounded, increasing the voltage drop between the drain and source. In the presence of the inversion region, the current between the drain and source increases. The resulting high electron flow from source to drain increases the kinetic energy of the electrons. This causes the electrons to gain enough energy to overcome the outside barrier and collect on the floating gate.
After the write is completed, the negative charge on the floating gate raises the transistor's threshold voltage (V
T
) above the wordline logic 1 voltage. When a written transistor's wordline is brought to a logic 1 during a read, the transistors will not turn on. Sense amplifiers detect and amplify the transistor current, and output a 0 for a written transistor.
The floating gate can be unprogrammed, or “erased,” by grounding the control gate and raising the source voltage to a sufficiently high positive voltage to transfer electrons out of the floating gate to the source terminal of the transistor by tunneling through the insulating gate oxide. After the erase is completed, the lack of charge on the floating gate lowers the cell's V
T
below the wordline logic 1 voltage. Thus when an erased cell's wordline is brought to a logic 1 during a read, the transistor will turn on and conduct more current than a written cell. Some flash devices use Fowler-Nordheim tunneling for write as well as erase.
One of the present hurdles to FLOTOX transistors replacing DRAMs concerns the Fowler-Nordheim (FN) erase operation. Fowler-Nordheim tunneling requires high voltages, is relatively slow, and introduces erratic over erase and other reliability problems due to the very high erase voltages used. These very high erase voltages are a fundamental problem arising from the high electron affinity of bulk silicon or large grain polysilicon particles used as the floating gate. The high electron affinity creates a very high tunneling barrier and, even with high negative voltages applied to the gate, a large tunneling distance. The high tunneling barrier and large tunneling distance equate to a very low tunneling probability for electrons attempting to leave the floating gate. This results in long write times since the net flux of electrons leaving the floating gate is low or the tunneling current discharging from the floating gate is low.
One method for FLOTOX transistors to overcome the high erase voltages and attain DRAM level operation voltages is through the use of textured or micro-roughened surfaces. Efforts have demonstrated that producing a textured surface at the substrate/tunnel oxide (Si/SiO
2
) interface increases the electric fields between the floating gate and the substrate. The higher electric field in turn produces higher tunneling currents at lower voltages. Previous work has achieved a textured surface formed as a dense array of microtips (i.e. 10
8
/cm
2
). The textured surfaces result in higher tunneling currents at lower voltages. However, these techniques require oxidation to form the insulating gate oxide after the texturing has been completed. This process is self defeating in that it tends to smooth the surface and remove the textured features.
Thus, what is needed is an improved method and structure for producing FLOTOX transistors which have high tunneling currents at low voltages. It is further desirable to attain these results with a device which satisfies the industry wide demand for high density devices.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, it is desirable to develop an improved method and structure for FLOTOX transistors.
SUMMARY OF THE INVENTION
The above mentioned problems with non volatile FLOTOX transistors and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A method and structure are provided which create an improved textured surface and improved insulating gate oxide in order to increase low voltage tunneling currents in FLOTOX transistors.
In particular, an illustrative embodiment of the present invention includes a non volatile memory cell structure. The non volatile memory cell structure includes a substrate with a textured surface. The textured surface includes an array of microtips with each microtip having a top surface. The microtips in the array have an average density of 10
12
/cm
2
. A tunnel oxide layer is adjacent to the textured substrate. The tunnel oxide layer is deposited using binary reaction sequence chemistry. A first gate is formed on the tunnel oxide layer. An insulator layer formed on the first gate. The structure further includes a second gate formed on the insulator layer.
In another embodiment, a non volatile memory cell structure is provided. The structure includes a first interface which has spaced source and drain regions and a body region located between the source and drain on a first portion of the interface. The first interface has a silicon (Si) layer adjacent to a silicon dioxide (SiO
2
) layer. The silicon dioxide (SiO
2
) layer has a thickness between 15 and 100 Angstroms (Å). The silicon dioxide (SiO
2
) layer is deposited using binary reaction sequence chemistry. A second interface is adjacent to the first interface. A third interface is adjace
Forbes Leonard
Geusic Joseph E.
Chaudhari Chandra
Micro)n Technology, Inc.
Schwegman, Lundberg Woessner & Kluth, P.A
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