Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2006-08-29
2006-08-29
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C438S401000
Reexamination Certificate
active
07098546
ABSTRACT:
The present invention pertains to utilizing a salicide in establishing alignment marks in semiconductor fabrication. A metal layer is formed over exposed portions of a silicon substrate as well as oxide areas formed over bitlines buried within the substrate. The metal layer is treated to react with the exposed portions of the silicon substrate to form salicided areas. The metal layer does not, however, react with the oxide areas. As such, salicided areas are formed adjacent to the oxide areas to provide an enhanced optical contrast when light is shined there-upon. In this manner, the alignment marks can be more readily “seen”. The enhanced optical contrast thus allows the marks to continue to be seen as scaling occurs.
REFERENCES:
patent: 6342426 (2002-01-01), Li et al.
patent: 6436766 (2002-08-01), Rangarajan et al.
patent: 2004/0145066 (2004-07-01), Swanson et al.
patent: 2004/0212009 (2004-10-01), Wang et al.
Wolf et al., Silicon Processing for the VLSI Era, vol. 2, 2nd edition, Lattice Press, 2000, pp. 268, 606-607, 726.
Lingunis Emmanuil H.
Shiraiwa Hidehiko
Yang Jean Yee-Mei
Doty Heather
Eschweiler & Associates LLC
Fasl LLC
Jr. Carl Whitehead
LandOfFree
Alignment marks with salicided spacers between bitlines for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Alignment marks with salicided spacers between bitlines for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Alignment marks with salicided spacers between bitlines for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3700674