Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-30
2001-05-29
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S278000
Reexamination Certificate
active
06238983
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of producing a semiconductor memory device, and more particularly to methods of producing a metal oxide semiconductor (MOS) read-only memory (ROM) device with shortened turn-around time.
2. Description of the Related Art
The fabrication of ROMs involves many process steps and ROMs are frequently made on special order, where the customer specifies the data that is to be stored or “implanted” in the ROM. In order to reduce the turn-around time (TAT) from when a customer places an order for ROMs to delivery, a manufacturer will prefabricate ROMs of certain storage capacities ahead of time and then store them (called banking). When a customer places an order, all the manufacturer now has to do is program the customer's data, by use of a mask, into the banked ROM and finish the chip. Therefore, the more processing steps can be done prior to banking, the fewer steps will be necessary afterwards and the less time it takes to deliver the chips. A description of masked ROMs is provided by S. Wolf in Silicon Processing for the VLSI Era, Volume 2—Process Integration, by Lattice Press, copyright 1990, Chapter 8.4, page 619.
Since the TAT is of significant economic impact and a factor in the competitiveness of a ROM supplier, there have been many proposals on how to shorten the TAT. In a typical process, called the implant code process, the code implant is done by converting selected transistors (the storage devices) of the ROM from enhancement to depletion mode devices, thereby turning the selected transistors on permanently. The unselected enhancement transistors can be viewed as storing logical “zeroes”, while the depletion mode transistors can be viewed as storing logical “ones”. The implant code process is usually through the sacrificial oxide (called SAC oxide) or the gate oxide of the selected transistors to transform the device cell from enhancement to depletion mode, however, shortening the cycle time is still an important economic goal.
FIG. 1
depicts a tiny portion a plan view of a prior art ROM memory
10
, showing an array of active areas represented by OD
1
and OD
2
and of poly lines represented by PO
1
, PO
2
, and PO
3
at right angles to the active areas. ROM cells are located at the intersection of active areas and poly lines. Depletion cell implant mask
11
extend over two cells and implant mask
12
extends over one cell. Arrows A indicate the area of the thinned field oxide and cell leakage.
FIG. 2
a
is a cross section, taken along line
2
a
-
2
a
of
FIG. 1
, before the dip back and implant profile step. Two cells
21
and
22
(on substrate
20
) are shown separated by a field oxide (FOX)
23
having a thickness much greater than 6500 Åangstrom. Each cell is shown with a polysilicon gate
24
and oxide
25
with sidewall spacers.
FIG. 2
b
illustrates the implant process step, depicted by arrows B, after the dip back step, i.e. the process of coding cells
21
and
22
. The field oxide loss caused by the post buffered oxide etch is indicated by dashed lines
27
within field oxide
23
. The field oxide loss causes a very undesirable cell leakage current. Photoresist
26
defines the area affected by the etchant, which equals the depletion cell implant mask
11
of FIG.
1
.
To further improve the TAT, a change in the implant procedure from “through the SAC oxide” to “through the poly gate” is necessary by adding a dip back and etch back process to enlarge the implant process window and to get the depletion cell function. However, the dip back process impacts the field oxide thickness and increase the cell leakage current and final testing would see an increased yield loss. Additionally, the lower implant energy and implant depth are ineffective in achieving a stable depletion mode device.
The following U.S. Patents either relate to the manufacture of ROMs or to the problems discussed above:
U.S. Pat. No. 5,792,697 (Wen) discloses a method of forming a multi-stage ROM, replacing a multiple code implant.
U.S. Pat. No. 5,681,772 (Chen et al.) teaches the use of a recessed dielectric region overlying a gate electrode region. This method allows for an implanting step to occur after the dielectric layer is applied to surface of the device. Coding during a later processing step shortens product TAT.
U.S. Pat. No. 5,514,609 (Chen et al.) is similar to U.S. Pat. No. 5,681,772.
U.S. Pat. No. 5,449,632 (Hong) describes a method of producing a ROM where word lines are formed after the code implant step.
U.S. Pat. No. 4,268,950 (Chatterjee et al.) presents a method of programming a ROM either after the top level of device interconnects has been patterned and sintered or after the electrical testing of the devices. Selected transistors are programmed by implanting ions through their gates and gate oxides into the silicon.
It should be noted that none of the above cited examples of the related art are based on the metal code process which is disclosed subsequently.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of improving the turn-around-time of a ROM from time of received order to product delivery.
Another object of the present invention is to avoid field oxide loss and thus prevent leakage current problems.
A further object of the present invention is to provide a stable depletion mode device character for the ROM cell.
These objects have been achieved by combining the alignment dip back procedure (to reduce the polyoxide thickness over selected gate electrodes and to protect the field oxide) with the double charge implant, where the implant species has an absolute charge greater than one electron volt and where the implanting step is at an energy greater than 150 keV.
REFERENCES:
patent: 4268950 (1981-05-01), Chatterjee et al.
patent: 4467520 (1984-08-01), Shiotari
patent: 5350703 (1994-09-01), Lee
patent: 5449632 (1995-09-01), Hong
patent: 5514609 (1996-05-01), Chen et al.
patent: 5681772 (1997-10-01), Chen et al.
patent: 5792697 (1998-08-01), Wen
S. Wolf, “Silicon Processing for the VLSI Era”, vol. 2: Process Integration, Lattice Press, Sunset Beach, CA, ©1990, p. 619.
Chu Cheng-Yu
Chu Yi-Jing
Lin Dean E.
Sheu Jenq-Dong
Ackerman Stephen B.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Tsai Jey
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