Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-05-31
2004-08-24
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S597000, C438S619000, C438S672000, C438S697000, C438S710000, C438S725000, C438S737000
Reexamination Certificate
active
06780753
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
Embodiments of the invention generally relate to a method for forming an air gap between conductive elements of a semiconductor device, wherein the air gap has a dielectric constant (k) of approximately 1.
2. Description of the Related Art
Reliably producing sub-quarter micron and smaller features on semiconductor substrates is a key technology for the next generation of very large scale integration (VLSI) and large-scale integration (ULSI) devices. However, as the fringes of circuit technology are advanced, the shrinking dimensions of the interconnect features places increasing demands on the processing techniques and the physical characteristics of the materials used to manufacture the devices. For example, in order to improve the density of semiconductor devices on integrated circuits, the size of features thereon has decreased to the sub-quarter micron range. Additionally, copper has essentially replaced aluminum as the primary conductor, primarily as a result of the lower resistivity provided by copper. Further, the shrinking dimensions have necessitated dielectric materials, i.e., the material positioned between the conductive features, having lower dielectric constants than previously utilized, i.e., low k, as defined herein, generally refers to dielectric constants of less than about 4.0, as the increased capacitive coupling between layers resulting from the closeness of the conductive elements can detrimentally affect the functioning of semiconductor devices.
A common method utilized to form the currently desired multilayer semiconductor devices is a damascene or dual damascene process. In a damascene method, for example, one or more low k dielectric materials are deposited and pattern etched to form the vertical and horizontal interconnects. Conductive materials, such as copper-containing materials and other conductive materials, such as barrier layer materials used to prevent diffusion of copper-containing materials into the surrounding low k dielectric material, are then inlaid into the etched pattern or features. These conductive materials are generally deposited in excess in order to insure that the features formed in the dielectric layer are adequately filled. However, the excess copper-containing materials and excess barrier layer material external to the etched pattern, such as on the field of the substrate, are generally removed via, for example, a chemical mechanical polishing process. Once the excess deposition is removed, the device generally has a substantially planar upper surface that includes the conductive and insulative elements exposed therefrom, and therefore, an insulating layer is generally deposited thereover to insulate the first layer of features from a second layer that may be deposited on top of the first layer.
However, one challenge associated with damascene processes is that the size of the individual features therein continues to decrease in order to accommodate the increasing circuit density. As a result thereof, the dielectric constant of the material separating the respective conductive elements must also decrease in order to maintain electrical isolation of the respective conductive elements. Although current low k dielectric materials may provide a k value of between about 2.0 and about 3.5, for example, materials having lower dielectric constants will be required in order to support the continuing decrease in feature sizes and increases in circuit density.
Therefore, there exists a need for a spacer to be used between conductive elements of a semiconductor device, wherein the spacer provides a dielectric constant below about 2.
SUMMARY OF THE INVENTION
Embodiments of the invention generally provide a method of forming an air gap between conductive elements of a semiconductor device, wherein the air gap has a dielectric constant of approximately 1. The air gap may generally be formed by depositing a dielectric material between the respective conductive elements, depositing a porous layer over the conductive elements and the dielectric material, and then stripping the dielectric material out of the space between the respective conductive elements through the porous layer, which leaves an air gap between the respective conductive elements. The dielectric material may be, for example, an amorphous carbon layer, the porous layer may be, for example, a porous oxide layer, and the stripping process may utilize a downstream hydrogen-based strip process, for example.
Embodiments of the invention may further provide a method for forming a low k spacer between conductive interconnects. The method generally includes forming interconnect features into a dielectric layer deposited on a substrate, wherein the dielectric layer is an amorphous carbon layer, and filling the interconnect features with a conductive material. The method further includes depositing a porous layer over the filled interconnect features and dielectric layer, the porous layer having an ordered pore structure and stripping the dielectric layer out of an area between the filled conductive interconnects through the porous layer to form an air gap between the conductive interconnects. Finally, the method may include depositing a capping layer over the porous layer to seal the ordered pore structure.
Embodiments of the invention may further provide a method for forming a spacer between conductive members of a semiconductor device. The method may generally include depositing a dielectric layer on a substrate, forming features into the dielectric layer, and filling the features with a conductive material. The method may further include depositing a porous layer over the filled interconnect features and dielectric layer, the porous layer having an ordered pore structure, stripping the dielectric layer out of an area between the filled conductive interconnects through the porous layer to form an air gap between the conductive interconnects, and depositing a capping layer over the porous layer to seal the ordered pore structure.
Embodiments of the invention may further provide a method for forming a spacer having a dielectric constant of about 1 between conductive features of a semiconductor device. The method may include depositing an amorphous carbon layer onto a substrate using a chemical vapor deposition process, etching features into the amorphous carbon layer, and filling the features etched into the amorphous carbon layer with a conductive material using at least one of an electrochemical plating process, an electroless plating process, a physical vapor deposition process, and a chemical vapor deposition process. Additionally, the method may include using a chemical mechanical polishing process to planarize an upper surface of the semiconductor device, depositing a porous oxide layer over the filled features and amorphous carbon layer, stripping the amorphous carbon layer from areas between conductive elements via a downstream hydrogen-based stripping process configured to remove the amorphous carbon layer through pores in the porous oxide layer, which operates to form an air gap between the conductive elements, and depositing a capping layer over the porous oxide layer to seal the pores.
Embodiments of the invention may further provide a method for forming a low k spacer between conductive interconnect features formed into a dielectric layer on semiconductor substrate. The method may include depositing a porous layer over the interconnect features and dielectric layer, removing at least a portion the dielectric layer out of an area between the conductive interconnect features through the porous layer to form an air gap between the conductive interconnect features, and depositing a capping layer over the porous layer to seal the porous layer. The resulting space between the interconnect features being filled with air, which generates a dielectric constant of about 1.
REFERENCES:
patent: 5324683 (1994-06-01), Fitch et al.
patent: 5407860 (1995-04-01), Stoltz et al.
patent: 5461003 (1995-10-01), Havemann et al.
patent: 556
Armacost Michael D.
Bencher Christopher D.
Latchford Ian S.
Ngai Christopher
Weidman Timothy
Applied Materials Inc.
Isaac Stanetta
Moser Patterson & Sheridan
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