Address signal generator in a semiconductor memory

Details Address signal generator in a semiconductor memory Address signal generator in a semiconductor memory

2000-08-24

2001-12-04

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S190000, C327S239000, C327S256000

Reexamination Certificate

active

06327191

ABSTRACT:

This Application claims the benefit of Koren Patent Application No. 99-35433 filed on Aug. 25, 1999, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, more particularly, to an address signal generator in a semiconductor memory which is capable of generating address signals with a high speed.
2. Discussion of Related Art
When a read or a write operation is controlled by a CPU in a semiconductor memory, there exists a timing margin, i.e., so-called set-up time and holding time, for performing synchronization with a clock. The set-up time is a time for confirming a data before the generation of a control signal. The holding time is a time during which the confirmed data maintains its state after the generation of the control signal.
FIG. 1
shows a circuit for an address signal generator in a semiconductor memory according to a related art.
Referring to
FIG. 1
, an address signal generator consists of NOR gates
108
and
112
and inverters
110
and
114
. In the address signal generator, an external address BXIN is transformed into address signals BXT and BXB. The external address BXIN is inputted to an inverter
102
. Then, the address BXIN is latched by a latch consisting of inverters
104
and
106
. An output of the inverter
102
is inputted to the NOR gate
112
. An output of the latch, i.e., the output of the inverter
104
, is inputted to the other NOR gate
108
. The inverter
102
and the inverter
106
of the latch are tri-state inverters which are enabled by an address enabling signal XAEI and its inverted signal.
The inverter
102
is enabled provided that the address enabling signal XAEI is at a low level. The inverter
106
of the latch is enabled when the address enabling signal XAEI is at a high level, thereby latching the external address BXIN inputted through the inverter
102
. Namely, during a period defined by the address enabling signal XAEI, the inputting and the latching operations of the external address BXIN are completed.
An inverted signal of the address enabling signal XAEI enables the inverter
106
of the latch as soon as it is inputted to the NOR gates
108
and
112
which actually generate an address. Thus, the output of an inverter
116
should be at a low level so that the outputs of the inverter
102
and the inverter
104
of the latch are outputted as the address signals BXT and BXB. Namely, the output of the inverter
116
which is an inverted signal of the address enabling signal XAEI enables the address signal generator as well.
Therefore, the outputs of the inverters
102
and
104
are outputted as the address signals BXB and BXT respectively while the output of the inverter
116
is at a low level (which means that the address enabling signal XAEI is at a high level).
FIG. 2
is a timing diagram showing operational characteristics of an address signal generator in a semiconductor memory according to a related art. In
FIG. 2
, t
1
is a set-up time. Referring to
FIG. 2
, an external address BXIN is first generated. Thereafter, address signals BXT and BXB are generated after a time interval t
3
following the time point at which an address enabling signal XAEI goes up to a high level.
Namely, the external address BXIN has been confirmed at first. After a predetermined time t
1
, the address enabling signal XAEI goes up to a high level. After the address enabling signal XAEI has gone to the high level, the logic value is maintained for a predetermined time t
2
. In this case, t
1
and t
2
represent the so-called set-up time and holding time, respectively.
The logic values of the address signals BXT and BXB are complementary to each other. BXT and BXB are at low and high levels respectively provided that the external address BXIN is at a low level. Otherwise, BXT and BXB are at high and low levels respectively provided that the external address BXIN is at a high level.
Once the address enabling signal XAEI goes to a low level, the address signals BXT and BXB are fixed to a high level regardless of the logic value of the external address BXIN.
As shown in
FIG. 2
, the address signals BXT and BXB are generated after a time of t
3
from a time point at which the address enabling signal XAEI has gone up to a high level. This is because it takes some time for the outputs of the NOR gates
108
and
112
in
FIG. 1
to be enabled by the address enabling signal XAEI.
FIG. 3
shows a circuit for generating an address enabling signal XAEI in a semiconductor memory according to a related art.
Referring to
FIG. 3
, four buffers
302
a
to
302
d
are connected in series and are used as delaying means which decide the value of ti (i.e., t
1
through t
3
shown in
FIG. 2
) by sizes of the delaying means. Namely, the size of ti is controlled by manipulating the sizes of the buffers
302
a
to
302
d.
A bank selection signal BANKi is inputted to the first buffer
302
a
and is enabled by a chip enabling signal ACT. An output of the fourth buffer
302
d
is the address enabling signal XAEI. The output of the buffer
302
d
may be outputted as a sense amplifier enabling signal SAE and a word line enabling signal WLE through other buffers
304
,
306
and
308
.
As mentioned in the above description, the delay of generating the address signals BXT and BXB by the address enabling signal XAEI hinders high-speed signals required for a high-speed system, memory devices, etc.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor memory that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an address signal generator in a semiconductor memory which prevents the delayed-generation of address signals by enabling the address signals BXT and BXB using an address signal generation enabling signal which is faster than the conventional address enabling signal, before the logic values of the address signals BXT and BXB are confirmed as the address enabling signal XAEI goes up to a high level.
Another object of the present invention is to provide an improved address signal generator in a semiconductor memory which is enabled by an address signal generation enabling signal produced by a bank selection signal and a chip enabling signal.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes an address signal generator for receiving an external address which is inputted by a first control signal and is latched by a second control signal wherein the address signal generator is enabled by a third control signal and generates complementary address signals in use of the latched signal.
In another aspect, the present invention includes a control signal generator for generating a first control signal controlling an input of an external address and a second control signal latching the inputted external address, a latch enabled by the second control signal and latching an output of a first inverter, and an address signal generator enabled by a third control signal wherein the address signal generator generates complementary address signals in use of outputs of the first inverter and the latch.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5047986 (1991-09-01), Miyamoto et al.
patent: 5949731 (1999-09-01), Tsukude

Affiliated with

Also associated with

Rating

Address signal generator in a semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Address signal generator in a semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Address signal generator in a semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2600117