Address controlled sense amplifier overdrive timing for semicond

Details Address controlled sense amplifier overdrive timing for semicond Address controlled sense amplifier overdrive timing for semicond

1999-03-19

2000-12-26

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365194, 365207, G11C 700

Patent

active

061669776

ABSTRACT:
A dynamic random access memory device having a number of sense amplifier banks (404a-404h) is disclosed. Each sense amplifier bank (404a-404h) has an associated memory array (402a-402h) and supply switch (406a-406h). In a given sense operation, data signals are coupled from a memory array (402a-402h) to its associated sense amplifier bank (404a-404h). Selection of the memory array (402a-402h) is determined by address signals (MS0-MS7). The supply switches (406a-406h) provide a sense amplifier supply voltage at a supply node (708) of its associated sense amplifier bank (404a-404h). At the initial portion of a sense operation, the supply switch (406a-406h) couples the high power supply voltage (VDD) to its associated supply node (708). After a predetermined time period, the supply switch couples a reduced array voltage (VDL) to its associated supply node (708). The switching operation is determined by an overdrive signal (SAOV). The timing of the SAOV signal is based upon the location of the memory array (402a-402h) which is being accessed in the sense operation.

REFERENCES:
patent: 5477498 (1995-12-01), Ooishi
patent: 5793689 (1998-08-01), Yoon et al.
patent: 6028812 (2000-02-01), Tanaka
patent: 6061278 (2000-05-01), Kato et al.

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