Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1996-10-18
2000-01-25
Hua, Ly V.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
365201, G01R 3128
Patent
active
060188154
ABSTRACT:
Scan chains to support debugging and manufacturing test modes for integrated circuit chips are made adaptable. Scan chains may be configured either in a multiple scan chain JTAG mode or in a multiple independent and parallel scan chain mode. The configuration transition between the scan modes is made by private instructions implemented in a JTAG controller, which supports the IEEE 1149.1 standard.
REFERENCES:
patent: 4860290 (1989-08-01), Daniels et al.
patent: 5280616 (1994-01-01), Butler et al.
patent: 5313470 (1994-05-01), Simpson
patent: 5329471 (1994-07-01), Swoboda et al.
patent: 5341096 (1994-08-01), Yamamura
patent: 5349587 (1994-09-01), Nadeau-Dostie et al.
patent: 5434804 (1995-07-01), Bock et al.
patent: 5448576 (1995-09-01), Russell
patent: 5479652 (1995-12-01), Dreyer et al.
patent: 5488688 (1996-01-01), Gonzales et al.
patent: 5497378 (1996-03-01), Amini et al.
patent: 5504756 (1996-04-01), Kim et al.
patent: 5510704 (1996-04-01), Parker et al.
patent: 5515382 (1996-05-01), Lassorie
patent: 5519715 (1996-05-01), Hao et al.
patent: 5524114 (1996-06-01), Peng
patent: 5535331 (1996-07-01), Swoboda et al.
patent: 5546568 (1996-08-01), Bland et al.
patent: 5592493 (1997-01-01), Crouch et al.
patent: 5608736 (1997-03-01), Bradford et al.
patent: 5614838 (1997-03-01), Jaber et al.
patent: 5623503 (1997-04-01), Rutkowski
patent: 5636227 (1997-06-01), Segars
patent: 5651013 (1997-07-01), Iadanza
patent: 5668481 (1997-09-01), Sheu et al.
patent: 5673276 (1997-09-01), Jarwala et al.
patent: 5675589 (1997-10-01), Yee
patent: 5680543 (1997-10-01), Bhawmik
Mark F. Lefebvre, Functional test and diagnosis: A proposed JTAG sample mode scan tester, 1990 International test conference, pp. 294-303, Jun. 1990.
Zacharia et al., Two dimensional test data decompressor for multiple scan designs, International test conference, Jun. 1996, pp. 186-194.
Texas Instruments, Boundary-Scan Architecture and IEEE Std 1149.1 (from Chapter 3 of TI's IEEE 1149.1 Testability Primer, SSYA002B) (Nov. 1996).
IEEE Computer Society, "IEEE Standard Test Access Port and Boundary-Scan Architecture", Published by the Institute of Electrical and Electronics Engineers, Inc. (1990), including 1149.1a (Oct. 21, 1993) and 1149.1b (Mar. 1, 1995).
Maunder and Tulloss, "The Test Access Port and Boundary-Scan Architecture", Published by the IEEE Computer Society Press, Los Alamitos, California (1990).
Hua Ly V.
Iqbal Nadeem
Samsung Electronics Co,. Ltd.
Shenker Michael
LandOfFree
Adaptable scan chains for debugging and manufacturing test purpo does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Adaptable scan chains for debugging and manufacturing test purpo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Adaptable scan chains for debugging and manufacturing test purpo will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2324069