Accelerated Galois data integrity crosscheck system and method

Details Accelerated Galois data integrity crosscheck system and method Accelerated Galois data integrity crosscheck system and method

2006-09-26

2006-09-26

Lamarre, Guy (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S799000

Reexamination Certificate

active

07114116

ABSTRACT:
The present invention permits error detection to be performed on a word basis (e.g., 32 bits in parallel). An exclusive OR function is performed on each bit of data and cyclic redundancy code (CRC) bit in parallel. If a feedback value (e.g., a standard poly divider) is a logical one it is also included in the exclusive OR function. The present invention is readily adaptable for use with a variety of CRC polynomials (e.g., any Galois Finited Field Equation with primitive irreducible polynomials over GF(2) with linearly independent roots and the reciprocal polynomial with linearly independent roots. In one embodiment, each data word is effectively multiplied by alpha to the first power, where alpha is a root solution to the applicable polynomial utilized to calculate the CRC. In one exemplary implementation of the present invention, the instructions are in assembly language configured with a machine instruction shift through carry.

REFERENCES:
patent: 4433388 (1984-02-01), Oosterbaan
patent: 4949342 (1990-08-01), Shimbo et al.
patent: 5020060 (1991-05-01), Murai et al.
patent: 5177747 (1993-01-01), Capps et al.
patent: 5303302 (1994-04-01), Burrows
patent: 5537421 (1996-07-01), Dujari et al.
patent: 5606662 (1997-02-01), Wisor
patent: 6374383 (2002-04-01), Weng
patent: 6704838 (2004-03-01), Anderson
patent: 6738947 (2004-05-01), Maeda
patent: 6766493 (2004-07-01), Hoffman et al.
patent: 6779150 (2004-08-01), Walton et al.
Wicker, Stephen B. Error Control Ststems for Digital Communication and Storage, Prentice Hall, pp. 100-123.
J. Zweig, et al., “TCP Altenate Checksum Options,” Mar. 1990, 5 pages.
Craig Partridge, et al., “Performance of Checksums and CRCs over Real Data,” 1995 ACM, pp. 68-76.
Jonathan Stone, et al., Performance of Checksums and CRC's over Real Data, 1998 IEEE, ACM Transaction on Networking, vol. 6, No. 5, pp. 529-543.
Anh Vu, “Error Detection and Error Correction,” Oct. 27, 1997, 7 pages.
Anastase Nakassis, “Fletcher's Error Detection Algorithm: How to Implement it Efficiently and How to Avoid the Most Common Pitfalls,” ACM SIGCOMM Computer Communication Review, vol. 18, Issue 5, Oct. 1998, pp. 63-88.
Anarchriz, “CRC and How to Reverse it: A CRC Tutorial & The c001 Way to Reverse CRC,” Apr. 1999, 14 pages.
“Cyclic Redundancy Check,” Aug. 2, 1997, 1 pages.
Eric Smith, “Memory Error Detection and Correction: An Introduction to Parity and ECC,” Aug. 23, 1996, 2 pages.
Timothy Hsu, “How to Select System Memory,” Jan. 9, 1999, 13 pages.
“Memory Tutorial,” 1998, 3 pages.
Satran, Sheinwald Informational, “iSCSI CRC Considerations,” May 7, 2001, 18 pages.
“A Short Spiel on 1-Bit Error Correction Codes,” printed Aug. 11, 2001, 2 pages.
Rick Kelly, “Error Management Using DesignWare CRC and ECC,” 2001 Synopsys, Inc., 5 pages.
ZDNet UK, “Parity RAM and ECC,” PC Magazine Guide to Servers, 1999, 1 page.
“Before you start—Chapter 6: Break and Verify,” © Laurence Soucy 1997/2001, 1 page.
“A Painless Guide to CRC Error Detection Algorithms,” Version 3.00, Sep. 24, 1996, 19 pages.

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