Abrupt delta-like doping in Si and SiGe films by UHV-CVD

Details Abrupt delta-like doping in Si and SiGe films by UHV-CVD Abrupt delta-like doping in Si and SiGe films by UHV-CVD

1997-06-30

2004-04-20

Mulpuri, Savitri (Department: 2812)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

C438S503000

Reexamination Certificate

active

06723621

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor films with steep doping profiles and more particularly to forming abrupt “delta-like” doping in thin layers from 5-20 nm thick suitable for Si or SiGe CMOS, modulation-doped field-effect transistors (MODFET's) devices, and heterojunction bipolar transistors (HBT's) using insitu doping in a ultra high vacuum-chemical vapor deposition (UHV-CVD) reactor.
BACKGROUND OF THE INVENTION
In-situ phosphorus doping in epitaxial Si and SiGe films or layers using PH
3
has been known to demonstrate a very slow incorporation rate of P due to the “poisoning effect” of phosphine on the Si(
100
) surface. An example of such a doping behavior is shown in
FIG. 1
by curve
11
. Curve portion
13
-
14
of curve
11
shows the slow “transient” trailing edge observed in the SIMS profile and corresponds to the slow incorporation rate of P into the silicon film. In
FIG. 1
the ordinate represents P concentration in atoms/cc and the abscissa represents depth in angstroms.
The incorporation of P into a Si layer is increased by the addition of a Ge containing gas (7%) along with phosphine in the reaction zone of a UHV-CVD reactor and has been described in U.S. Pat. No. 5,316,958 which issued May 31, 1994 to B. S. Meyerson and assigned to the assignee herein. The phosphorus dopant was incorporated during UHV-CVD in the proper substitutional sites in the silicon lattice as fully electrically active dopants. The amounts of Ge used were small enough that the primary band gap reduction mechanism in the presence of the n-type dopants at relatively high levels instead of the effect of the Ge. In U.S. Pat. No. 5,316,958 FIG. 2 shows phosphorus being incorporated into a Si layer during UHV-CVD with and without the addition of 7% Ge containing gas. With 7% Ge containing gas, a decade increase in P concentration would be incorporated in 250 to 500 Å into a silicon layer as shown, for example, by the rate of incorporation from 7×10
18
atoms/cc to 5×10
19
atoms/cc in FIG. 2 of '958.
Another well known problem associated with in-situ phosphorus or boron doping in silicon CVD is its “memory effect” as shown by curve portion
15
-
16
in
FIG. 1
for the case of phosphorus herein which tends to create an undesirable high level of dopant in the background due to its “autodoping behavior”. This “memory effect” is also evident in the SIMS analysis shown in FIG.
1
. The “memory effect” corresponds to a very slow fall or decrease in the phosphorus concentration which stems from a residual background autodoping effect. Hence, in-situ doping typically generates a undesirable “smearing out” of the dopant profile in silicon films formed by CVD.
FIG. 2
shows curve
11
which is the same as shown FIG.
1
and which illustrates the doping profile of the prior art using PH
3
. Curve
20
shows a desired or targeted profile having a width of 100 angstroms. In
FIG. 2
, the ordinate represents P concentration in atoms/cc and the abscissa represents depth in angstroms. Curve
11
has a dopant profile of at least 5 times wider or thicker than the targeted profile of 100 Angstroms in width or in depth as shown by curve
20
.
As device dimensions shrink and especially for future complementary metal oxide semiconductor (CMOS) logic, MODFET's, and HBT's incorporating SiGe layers, very thin layer structures having a width or thickness of 5-20 nm of high doping P concentrations will be needed which are impossible to obtain with present technology at this point using present ultra high vacuum-chemical vapor deposition (UHV-CVD) or standard silicon CVD processing.
SUMMARY OF THE INVENTION
In accordance with the present invention, a structure is provided having an increasing or decreasing abrupt doping profile comprising a substrate such as Si or SiGe having an upper surface, a first epitaxial layer of substantially Ge formed over the upper the first layer having a thickness in the range from 0.5 to 2 nm and doped e.g. with phosphorus or arsenic to a level of about 5×10
19
atoms/cc, and a second epitaxial layer of a semiconductor material having any desired concentration of dopants. The second layer may be Si or Si
1−x
Ge
x
. The concentration profile from the edge or upper surface of the first layer to 40 Å into the second layer may change by greater than 1×10
19
dopant atoms/cc.
The invention further provides a method comprising the steps of selecting a substrate having an upper surface, growing a first epitaxial layer of substantially Ge thereover less than its critical thickness and doped with phosphorus to a level of about 5×10
19
atoms/cc, growing a second epitaxial layer selected from the group consisting of Si and SiGe, the second epitaxial layer having any desired doping profile. The presence of the epitaxial Ge layer accelerates the incorporation rate of the P or As doping into the Ge layer, thereby eliminating the slow transient behavior. The initial, in-situ doping level is determined by the dopant flow in SCCM of the PH
3
/He mixture. The final overall doping profile may be controlled as a function of 1/GR where GR is the growth rate of the first and second layer. The dopant may be supplied or carried by phosphine (PH
3
) or Tertiary Butyl Phosphine (TBP) gas in the case of P and AsH
3
, or Tertiary Butyl Arsine (TBA) in the case of As in a UHV-CVD reactor.
To eliminate background “autodoping effect”, the structure phosphorus doping as shown in
FIG. 3
is transferred to a load chamber or load lock, while the growth chamber is purged of the background phosphorus. This growth/interrupt/growth process involves hydrogen flushing of the UHV-CVD reactor during interrupt. Then, a coating of Si or SiGe is grown on the sidewalls and/or heated surfaces of the UHV-CVD reactor at high temperature to isolate, eliminate or cover the residual phosphorus atoms prior to reintroducing the structure for further deposition. Alternatively, a second growth chamber i.e. UHV-CVD reactor coupled to the load chamber may be used where further undoped layers may be deposited with very low levels of phosphorus.
A second epitaxial layer
40
and/or a third epitaxial layer
44
of Si or SiGe shown in
FIG. 3
may now be grown with a background doping profile that drops or decreases to less than 5×10
16
atoms/cc after a 300 Å film is grown over layer
36
of structure
30
shown in FIG.
3
.
The invention further provides a method for forming abrupt doping comprising the steps of forming a layered structure of semiconductor material, selectively amorphizing a first layer having a high Ge content greater than 0.5, and crystallizing the amorphized first layer by solid phase regrowth. The amorphized first layer may be formed by ion implantation.
The invention further provides a field effect transistor a single crystal substrate having source and drain regions with a channel there between and a gate electrode above the channel to control charge in said channel and a first layer of Ge less than the critical thickness doped with a dopant of phosphorus or arsenic positioned below the channel and extending through the source and drain regions.
The invention further provides a field effect transistor comprising a single crystal substrate, a first layer of Ge less than the critical thickness formed on the substrate and doped with a dopant of phosphorus or arsenic, a second layer of undoped SiGe epitaxially formed on the first layer, a third layer of strained undoped semiconductor material of Si or SiGe, a source region and a drain region with a channel therebetween and a gate electrode above the channel to control charge in the channel.
The invention further provides a field effect transistor comprising a single crystal substrate, an oxide layer formed on the substrate having an opening, a gate dielectric and a gate electrode formed in the opening over the substrate, a source and drain region formed in the substrate aligned with respect to the gate electrode, a dielectric sidewall spacer formed on either side of the

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