High-speed data input circuit for a synchronous memory device

Details High-speed data input circuit for a synchronous memory device High-speed data input circuit for a synchronous memory device

1997-12-22

1999-07-06

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365192, 365233, 365239, G11C 1604

Patent

active

059205113

ABSTRACT:
A data input circuit for a semiconductor memory device uses an echo clock generator to reduce the clock cycle time. The echo clock is transmitted in the memory device with the data, thereby reducing the effects of clock skew and increasing the overall device operation speed. The circuit is particularly applicable to double data rate synchronous DRAM (DDR-SDRAM) circuitry.

REFERENCES:
patent: 5610864 (1997-03-01), Manning

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