TTL to CMOS input buffer circuit

Details TTL to CMOS input buffer circuit TTL to CMOS input buffer circuit

1989-08-21

1991-01-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451279, H03K 19092, H03K 19094, H03K 19017, H03K 17284

Patent

active

049888978

ABSTRACT:
A TTL to CMOS buffer includes a PMOS transistor and an NMOS transistor connected in series between Vcc and Vss. The buffer input is applied to the gate of both the PMOS and the NMOS transistor, and the buffer output is provided from the point of connection between the PMOS and the NMOS transistor. At least one other PMOS transistor has one current electrode connected to Vcc and a current electrode connected by a switch to the point of connection between the first PMOS and the NMOS transistor. At least one NMOS transistor has one current electrode connected to VSS and a current electrode connected by another switch to the point of connection between the first PMOS and the first NMOS transistor. Each switch is controlled by respective control signal generated by a temperature detecting circuit; each control signal is indicative of whether the device temperature is above or below a different predetermined level. There is a plurality of pairs of a MOS transistor set to be operated in the subthreshold region as a current supply, and a polycrystalline source of resistance serially connected to the MOS transistor between Vcc and Vss. The voltage from the point of connection between the MOS transistor and the resistor in each such pair is passed through a digital converter to provide a switching signal which controls a corresponding switch.

REFERENCES:
patent: 4437024 (1984-03-01), Wacyk
patent: 4628218 (1986-12-01), Nakaizumi
patent: 4698526 (1987-10-01), Allan
patent: 4916337 (1990-04-01), Leung et al.
patent: 4929853 (1990-05-01), Kim et al.

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