Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-12-29
1999-10-26
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438559, H01L 218247
Patent
active
059727527
ABSTRACT:
A method for forming a flash memory cell structure comprising the steps of providing a semiconductor substrate, and then sequentially forming a bottom conductive layer and a cap oxide layer over the substrate. Next, a pattern is defined in the conductive layer and the cap oxide layer. Subsequently, a thermal oxidation method is used to form a silicon oxide layer on the sidewalls of the bottom conductive layer. Then, a gate oxide layer is formed between the bottom conductive layers above the substrate. Thereafter, source/drain regions are formed in the semiconductor substrate. Then, spacer structures are formed adjacent to the silicon oxide layers. Using the spacer structures as masks, a portion of the gate oxide layer is etched. Then, the spacer structures are removed to expose the gate oxide layer. Next, a thermal oxidation method is used to form a tunneling oxide layer in the narrow region between the gate oxide layer. The tunneling oxide layer has a long narrow top profile. Finally, a floating gate layer, a dielectric layer and a control gate are sequentially formed to complete the flash memory cell structure.
REFERENCES:
patent: 5516713 (1996-05-01), Hsue et al.
patent: 5744391 (1998-04-01), Chen
patent: 5817557 (1998-10-01), Baldi
Chaudhari Chandra
United Semiconductor Corp.
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