Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Precharge

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Details

365149, 365204, G11C 700

Patent

active

056663188

ABSTRACT:
After performing high speed sensing with shutting off digit line pair, in which digit line is connected to an objective memory cell for access, only the digit line which is connected to the memory cell is electrically connected to the sense amplifier to perform re-writing of information to the memory cell by the corresponding sense amplifier. In subsequent balancing and pre-charging process, pre-charging is performed after sufficient balance of potential is established in the digit line pairs. By this, no extra charging current will flow in the digit line and/or the pre-charging power source to reduce power consumption.

REFERENCES:
patent: 5351215 (1994-09-01), Tanabe
patent: 5469395 (1995-11-01), Kuwabara et al.

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