Vertical NPN transistor for 0.35 micrometer node CMOS logic tech

Details Vertical NPN transistor for 0.35 micrometer node CMOS logic tech Vertical NPN transistor for 0.35 micrometer node CMOS logic tech

1997-04-11

2000-02-29

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438203, H01L 218249

Patent

active

060308648

ABSTRACT:
A method of fabricating a bipolar transistor concurrently with an MOS device comprising the steps of forming an NPN bipolar transistor by providing a semiconductor wafer (1) having a semiconductor region (3) of predetermined conductivity type having a surface. An emitter region (33) and a collector contact region (35) are formed in and extend to the surface of the semiconductor region (3) of predetermined conductivity type with an implant of the predetermined conductivity type. An intrinsic base region (43) is formed extending to the surface by implanting an impurity of opposite conductivity type in the semiconductor region (3) isolating the emitter region (33) from the semiconductor region of predetermined conductivity type. An insulating layer (49) is formed on the semiconductor region of predetermined conductivity type extending over all transitions at the surface of the predetermined conductivity type to the opposite conductivity type. A portion of the intrinsic base region (43) is then converted to an extrinsic base region (43). A portion of the collector contact (35), a portion of the emitter region (33) and a portion of the extrinsic base region (43) extend to the surface and an electrically conductive silicide (61) is formed at the surface on each of the collector contact (35), emitter region (33) and extrinsic base region (43). A CMOS device is formed in the wafer (1) concurrently with the fabrication of the bipolar transistor.

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