Method of fabricating interpoly dielectric layer of embedded dyn

Details Method of fabricating interpoly dielectric layer of embedded dyn Method of fabricating interpoly dielectric layer of embedded dyn

1998-05-07

2000-08-22

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438253, 438649, H01L 218242

Patent

active

061071315

ABSTRACT:
A method of fabricating an interpoly dielectric layer of an embedded DRAM wherein a substrate having a logic FET is provided and the logic FET has a source/drain region where a titanium suicide layer is formed thereon. An oxide layer is formed on the substrate and a silicion nitride layer is formed by PECVD on the oxide layer. The thermal stability can be improved because the formation of the compressive silicon nitride layer and the oxide layer prevents junction leakage, which is produced from the embedded DRAM.

REFERENCES:
patent: 5808335 (1998-09-01), Sung
patent: 5858831 (1999-01-01), Sung

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