Method of manufacturing DRAM capacitor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438254, 438396, 438397, H01L 218242

Patent

active

060872160

ABSTRACT:
A method of manufacturing a DRAM capacitor utilizes spacers to form a self-aligned node contact, and thus is able to reduce the cross-sectional dimensions of the node contact. Moreover, the spacers are capable of protecting any portion of a bit line that may be exposed due to misalignment when contact opening is formed. Hence, short-circuiting of the device can be prevented. Furthermore, by shaping the lower electrode of the capacitor into a fork-shaped structure with four prongs, the surface area for capacitor coupling is increased, thus increasing the capacitance of the capacitor, as well.

REFERENCES:
patent: 5464787 (1995-11-01), Ryou
patent: 5468670 (1995-11-01), Ryou
patent: 5571742 (1996-11-01), Jeong
patent: 5688726 (1997-11-01), Kim

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