Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-02-23
1999-08-24
Trinh, Michael
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438153, 438212, 438585, 438151, 438166, 438268, H01L 21336
Patent
active
059435747
ABSTRACT:
A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of semiconductor devices. Insulated gate contacts are spaced vertically from the terminals so as to define vertical vias and polysilicon is deposited in the vias to form conduction channels. An upper portion of the polysilicon in the vias is doped to form second terminals for the semiconductor devices, and the polysilicon is annealed to convert it to single grain polysilicon. A second electrically conductive layer is deposited and patterned on the second terminal to define second terminal contacts of the semiconductor devices.
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Goronkin Herbert
Shiralagi Kumar
Tehrani Saied N.
Hightower Robert F.
Motorola Inc.
Parsons Eugene A.
Trinh Michael
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