Scan-enabled method and system for testing a system-on-chip

Details Scan-enabled method and system for testing a system-on-chip Scan-enabled method and system for testing a system-on-chip

2009-07-16

2011-11-01

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S700000

Reexamination Certificate

active

08051347

ABSTRACT:
Scan-enabled method and system for testing a system-on-chip (SoC). The method includes electronically determining a slack in a signal at each port of a core of the SoC. The SoC includes multiple cores. Each core includes input ports and output ports. The method also includes selecting flip-flops for each port if the slack does not exceed a slack threshold. Further, the method includes integrating a wrapper cell to each port for which the slack exceeds the slack threshold. Moreover, the method includes coupling integrated wrapper cells and selected flip-flops corresponding to the input ports to form at least one input scan chain for the core, and corresponding to the output ports to form at least one output scan chain for the core. The method also includes testing the SoC using the at least one input scan chain and the at least one output scan chain of each core.

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