Digital delay locked loop circuit using mode register set

Details Digital delay locked loop circuit using mode register set Digital delay locked loop circuit using mode register set

2007-12-28

2011-11-22

Butler, Dennis M (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S503000

Reexamination Certificate

active

08065550

ABSTRACT:
A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator for reflecting in the data clock a value of subtracting an output of the delay time calculator from the information established in the mode register set.

REFERENCES:
patent: 2005/0035799 (2005-02-01), Mikhalev et al.
patent: 2005/0128828 (2005-06-01), Lee
patent: 2007/0008791 (2007-01-01), Butt et al.
patent: 10-1997-0077998 (1997-12-01), None
patent: 10-0728971 (2007-06-01), None

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