Semiconductor memory device and test method thereof

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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Reexamination Certificate

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08036052

ABSTRACT:
Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

REFERENCES:
patent: 7546497 (2009-06-01), Jang
patent: 2004/0246801 (2004-12-01), Lee et al.
patent: 20020080088 (2002-10-01), None
patent: 1020030056117 (2003-07-01), None
patent: 1020040093801 (2004-11-01), None
patent: 1020040104903 (2004-12-01), None
patent: 1020060015208 (2006-02-01), None
patent: 1020060121523 (2006-11-01), None
Korean Office Action dated Feb. 21, 2008 for corresponding Korean Application KR 10-2007-0018053.
Korean Notice of Allowance dated May 26, 2009 for corresponding Korean Patent Application No. 10-2007-0018053.

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