Methods for forming a transistor

Details Methods for forming a transistor Methods for forming a transistor

2008-07-29

2010-11-16

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21431

Reexamination Certificate

active

07833869

ABSTRACT:
Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon carbide material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon carbide material to form a source/drain region having a second conductivity.

REFERENCES:
patent: 5168072 (1992-12-01), Moslehi
patent: 6121100 (2000-09-01), Andideh et al.
patent: 6403482 (2002-06-01), Rovedo et al.
patent: 6566254 (2003-05-01), Mikagi et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 7413957 (2008-08-01), Nouri et al.
patent: 2002/0053711 (2002-05-01), Chau et al.
patent: 2002/0190284 (2002-12-01), Murthy et al.
patent: 2003/0080361 (2003-05-01), Murthy et al.
patent: 2003/0098479 (2003-05-01), Murthy et al.
patent: 2004/0033678 (2004-02-01), Arghavani et al.
patent: 2004/0070035 (2004-04-01), Murthy et al.
patent: 2004/0084735 (2004-05-01), Murthy et al.
Notification of First Office Action dated Aug. 1, 2008 for Chinese Patent Application No. 2005800058321.
International Search Report and Written Opinion for International Application No. PCT/US2005/019328 dated Aug. 14, 2006.
Partial International Search Report for International Application No. PCT/US2005/019328 dated Jul. 6, 2006.
Ghani, et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,” pp. 11.6.1-11.6.3, IEEE 2003.
Nouri, et al., A Systematic Study of Trade-Offs in Engineering a Locally Strained pMOSFET, IEDM Technical Digest. IEEE International 13-15. Dec. 2004, pp. 1055-1058.
P.R. Chidambaram article, 35% Drive Current Improvement from Recessed-SiGe Drain Extensions on 37 nm Gate Length PMOS. 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 48-49.
S. Thompson et al. article, “A 90 nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 Layers of Cu Interconnects, Low k ILD, and 1 um2 SRAM Cell” 2002 IEEE.
Scott E. Thompson Article, “A Logic Nanotechnology Featuring Strained-Silicon,” IEEE Electron Device Letter, vol. 25, No. 4, pp. 191-193, Apr. 2004.
Victor Chan article, “High Speed 45nm Length CMOSFETs Integrated Into a 90nm Bulk Technology Incorporating Strain Engineering”, 2003 IEEE, pp. 3.8.1-3.8.4.
Yang article, “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations”, 2003 IEEE.

Affiliated with

Also associated with

Rating

Methods for forming a transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for forming a transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for forming a transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4237809