Method for testing semiconductor integrated circuit and...

Details Method for testing semiconductor integrated circuit and... Method for testing semiconductor integrated circuit and...

2006-06-02

2009-06-02

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07543206

ABSTRACT:
A method is provided for testing a semiconductor integrated circuit by utilizing a scan path circuit provided to detect the degeneracy fault in the semiconductor integrated circuit, and bringing scan chains to states in which shift resistor operations can be effected for the input of patterns by which a glitch fault and the IR-DROP fault between the scan chains can be detected.

REFERENCES:
patent: 2002/0124218 (2002-09-01), Kishimoto
patent: 2005/0193300 (2005-09-01), Matsumoto et al.
patent: 2002257903 (2002-09-01), None

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