Sidewall spacer pullback scheme

Details Sidewall spacer pullback scheme Sidewall spacer pullback scheme

Filed on

2007-03-27

Date issued

2009-12-29

Examiner

Chaudhari, Chandra (Department: 2891)

Patent Class

Semiconductor device manufacturing: process

SubClass

Making field effect device having pair of active regions...

SubSubClass

Having insulated gate

Other Related Categories

C438S595000, C257SE21626

Type

Reexamination Certificate

Status

active

Patent number

07638402

Description

ABSTRACT:
A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.

REFERENCES:
patent: 6153485 (2000-11-01), Pey et al.
patent: 6610571 (2003-08-01), Chen et al.
patent: 6812091 (2004-11-01), Gruening et al.
patent: 6991979 (2006-01-01), Ajmera et al.
patent: 7074692 (2006-07-01), Chen et al.
patent: 2002/0076907 (2002-06-01), Rodder
patent: 2005/0215017 (2005-09-01), Chen et al.

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