Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2007-04-27
2009-06-09
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S154000
Reexamination Certificate
active
07545690
ABSTRACT:
A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.
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Kao Jerry C.
Kuang Jente B.
Ngo Hung Cai
Nowka Kevin J.
Elms Richard
Harris Andrew M.
Harris, Atty at Law, LLC Mitch
International Business Machines - Corporation
King Douglas
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