Interconnect array formed at least in part with repeated...

Details Interconnect array formed at least in part with repeated... Interconnect array formed at least in part with repeated...

2009-02-02

2009-10-27

Le, Thao X (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257SE23010, C438S666000

Reexamination Certificate

active

07608931

ABSTRACT:
An interconnect array formed at least in part using repeated application of an interconnect pattern is described. The interconnect pattern has at least ten interconnect locations. One of the ten interconnect locations is for a power interconnect. Another one of the ten interconnect locations is for a ground interconnect. At least eight interconnect locations remaining are for additional interconnects. The at least eight remaining interconnect locations are disposed around a medial region, where either the ground interconnect or the power interconnect is located in the medial region. An offset region has one of either the ground interconnect or the power interconnect not in the medial region. The interconnect array is at least partially formed by repeated application of the interconnect pattern offset from one another responsive to the offset region.

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