Processor with variable wake-up and sleep latency and method...

Details Processor with variable wake-up and sleep latency and method... Processor with variable wake-up and sleep latency and method...

2006-03-13

2009-08-04

Du, Thuan N (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power sequencing

C713S323000

Reexamination Certificate

active

07571335

ABSTRACT:
For a processor having a plurality of sequential stages, variable (or idiosyncratic) wake-up latencies and a method for managing power in such a processor are provided. Each sequential stage includes one or more logic blocks and one or more power switches. A power controller can measure wake-up latencies for the logic blocks and control the power switches of the logic blocks by referring to the measured wake-up latencies, respectively.

REFERENCES:
patent: 6609209 (2003-08-01), Tiwari et al.
patent: 7137021 (2006-11-01), Dhong et al.
patent: 2002/0002664 (2002-01-01), Kuermerle
patent: 2003/0005340 (2003-01-01), Ku
patent: 2003/0105984 (2003-06-01), Masuyama et al.
patent: 0284276 (1988-09-01), None
Search and Examination Report for corresponding GB Application No. 0605116.3 dated Jul. 20, 2006.

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