Serial ferroelectric random access memory architecture to equali

Details Serial ferroelectric random access memory architecture to equali Serial ferroelectric random access memory architecture to equali

1997-02-28

1999-06-15

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365145, 36523008, 365236, G11C 700

Patent

active

059128461

ABSTRACT:
An architecture for a serial ferroelectric memory device that incorporates the provision of a latch intermediate the device memory array and column decoder of a width equal to a row in the array. In operation, the presence of the latch ensures that each write access to the memory device loads a row into the latch. Data is then modified while retained in the latch and written back to the memory array at the end of the cycle. A read operation can perform a write-back from the latch to the memory array at the beginning of the cycle after data is loaded into the latch. The addition of the latch intermediate the column decoder and the memory array then serves to ensure that for typical block read operations each column of the memory array will experience the same single write back cycle. As a consequence, data retention reliability for the memory device is improved by mitigating the effects of disparate imprint on the memory cells of the memory array.

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"FM25160 Fram.RTM. Serial Memory Product Specification," .COPYRGT.1994 Ramtron International Corporation, 1850 ramtron Drive, Colorado Springs, CO 80921, pp. 2-34 through 2-40.

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