Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-07-20
2009-06-30
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000, C714S729000, C716S030000, C716S030000
Reexamination Certificate
active
07555687
ABSTRACT:
Each portion of an integrated circuit is tested using Automatic test pattern generation (ATPG) technique to detect intra-portion faults. Inter-portion faults are detected by first forming a scan chain containing (a) the memory elements in the fan-out of the inputs to each of said plurality of portions, (b) the memory elements in the fan-in of the outputs of each of said plurality of portions, (c) memory elements connected to combinatorial logic propagating data inputs to the memory elements of (a), and (d) memory elements connected to provide control signals to (a), (b) and (c). Sequential scan tests are then performed on the scan chain thus formed.
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Thirunavukarasu Senthil Arasu
Varadarajan Devanathan
Brady III Wade James
Britt Cynthia
Merant Guerrier
Stephens Dawn V.
Telecky , Jr. Frederick J.
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