Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-01-27
2008-10-21
Torres, Joseph D (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07441168
ABSTRACT:
The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor integrated circuit using a fault list corresponding to information on sites in the semiconductor integrated circuit where a fault is likely to occur or information required to reduce such faults. In addition, the fault detecting method and the layout method perform ordering of faults with their likelihood and weighting of the faults, taking into consideration physical information on a mask pattern within a chip or records of actual use of cells or functional blocks.
REFERENCES:
patent: 4204633 (1980-05-01), Goel
patent: 4769817 (1988-09-01), Krohn et al.
patent: 5257268 (1993-10-01), Agrawal et al.
patent: 5325309 (1994-06-01), Halaviati et al.
patent: 5414716 (1995-05-01), Bershteyn
patent: 5544308 (1996-08-01), Giordano et al.
patent: 5581475 (1996-12-01), Majors
patent: 5587930 (1996-12-01), Hori et al.
patent: 5640403 (1997-06-01), Ishiyama et al.
patent: 5663967 (1997-09-01), Lindberg et al.
patent: 5737340 (1998-04-01), Tamarapalli et al.
patent: 5825191 (1998-10-01), Nijima et al.
patent: 6044208 (2000-03-01), Papadopoulou et al.
patent: 6066179 (2000-05-01), Allan
patent: 6067651 (2000-05-01), Rohrbaugh et al.
patent: 6567946 (2003-05-01), Nozuyama
patent: 6618830 (2003-09-01), Balachandran
patent: 7065690 (2006-06-01), Yoshida et al.
patent: 61-175737 (1986-08-01), None
patent: 01-235872 (1989-09-01), None
patent: 07-098365 (1995-04-01), None
patent: 09-080121 (1997-03-01), None
patent: 09-264938 (1997-10-01), None
patent: 11-025147 (1999-01-01), None
patent: 11-087519 (1999-03-01), None
patent: 11-258313 (1999-09-01), None
patent: 11-265980 (1999-09-01), None
Ruiz, G., Mitchell, J.; Buron, A.; Switch-level fault detection and diagnosis environment for MOS digital circuits using spectral techniques; IEE Proceedings E [see also Computers and Digital Techniques, IEE Proceedings] Computers and Digital Techniques, Jul. 1992.
Mahlstedt, U.; Alt, J.; Hollenbeck, I.; Deterministic test generation for non-classical faults on the gate level; Proceedings of the Fourth Asian Test Symposium, Nov. 23-24, 1995, pp. 244-251.
Smith, D.T.; Johnson, B.W.; Profeta, J.A., III: System dependability evaluation via a fault list generation algorith; IEEE Transactions on Computers, vol. 45, Issue 8, Aug. 1996, pp. 974-979.
Defect-Based Test: A Key Enabler for Successful Migration to Structural Test, Intel Technology Journal Q1 '99, pp. 1-14.
“Improved Method for Weighted Random Pattern Weight Generation”, IBM Technical Disclosure Bulletin, May 1992, US, NN9205250.
Shimoda Reisuke
Yoshida Takaki
Matsushita Electric - Industrial Co., Ltd.
Steptoe & Johnson LLP
Torres Joseph D
LandOfFree
Fault detecting method and layout method for semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fault detecting method and layout method for semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fault detecting method and layout method for semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4019832