Trench FET with improved body to gate alignment

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S424000, C438S524000, C438S525000, C257SE21147, C257SE21419, C257SE21655

Reexamination Certificate

active

07416948

ABSTRACT:
A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.

REFERENCES:
patent: 6274437 (2001-08-01), Evans
patent: 6802719 (2004-10-01), Finney
patent: 2005/0242411 (2005-11-01), Tso
patent: 2007/0032020 (2007-02-01), Grebs et al.
patent: 2007/0069324 (2007-03-01), Takaishi

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