Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-08-31
2008-10-07
Lebentritt, Michael S. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S221000, C438S424000, C438S433000, C438S435000, C438S758000, C438S386000, C438S296000, C257S622000, C257S077000, C257SE21546
Reexamination Certificate
active
07432148
ABSTRACT:
Methods of forming an improved shallow trench isolation (STI) region are disclosed. Several exemplary techniques are proposed for treating STI sidewalls to improve the silicon (Si) surface at the atomic level. Each of the exemplary methods creates a smooth STI sidewall surface, prior to performing oxidation, by reconstructing silicon atoms at the surface. The suggested STI region can be used in imager pixel cells or memory device applications.
REFERENCES:
patent: 5573973 (1996-11-01), Sethi et al.
patent: 6333598 (2001-12-01), Hsu et al.
patent: 6495424 (2002-12-01), Kunikiyo
patent: 6660613 (2003-12-01), Kim et al.
patent: 6979878 (2005-12-01), Gardner et al.
patent: 2004/0014296 (2004-01-01), Kwak et al.
H.K. Kwon et al., IEEE Trans. Electron Devices, vol. 51, 178 (2004).
J. Nara et al., Phys. Rev. Lett. 79, 4421 (1997).
Kauffman Ralph
Li Jiutao
Mauritzson Richard A.
Ahmadi Mohsen
Dickstein & Shapiro LLP
Lebentritt Michael S.
Micro)n Technology, Inc.
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