Scan tests tolerant to indeterminate states when employing...

Details Scan tests tolerant to indeterminate states when employing... Scan tests tolerant to indeterminate states when employing...

Filed on

2006-03-29

Date issued

2008-07-22

Examiner

Ton, David (Department: 2117)

Patent Class

Error detection/correction and fault detection/recovery

SubClass

Pulse or data error handling

SubSubClass

Digital logic testing

Other Related Categories

C714S732000, C714S738000

Type

Reexamination Certificate

Status

active

Patent number

07404126

Description

ABSTRACT:
Scan tests tolerant to indeterminate states generated in an integrated circuit (IC) when employing signature analysis to analyze test outputs. Bits with indeterminate-state are masked when scanning out the bits from the scan chains to force such indeterminate bits to a known logic level. This prevents a signature generator receiving the outputs of a scan test from generating an invalid signature. In an embodiment, masking information is stored in encoded form in a memory. A decoding circuit decodes the masking information and provides mask data under control from a mask controller. Mask data is sent to a masking circuit which also receives corresponding bits from scan-out vectors, with each scan-out vector being generated by a corresponding one of multiple scan chains. The output of the masking circuit may be provided in a compressed form to the signature generator circuit.

REFERENCES:
patent: 5528610 (1996-06-01), Edler et al.
patent: 7131046 (2006-10-01), Volkerink et al.
patent: 7197681 (2007-03-01), Dervisoglu et al.
patent: 7266746 (2007-09-01), Hiraide
Subhasish Mitra, Michael Mitzenmacher, Steven S. Lumetta and Nishant Patil, “X-Tolerant Test Response Compaction” from IEEE CS and the IEEE CASS, IEEE Design & Test of Computers, Nov.-Dec. 2005.

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