Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-12-20
2008-03-04
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S591000, C257SE21209, C257SE21681
Reexamination Certificate
active
07338863
ABSTRACT:
Example embodiments of the present invention disclose a non-volatile semiconductor memory device, which may include a dielectric layer having an enhanced dielectric constant. A tunnel oxide layer pattern and a floating gate may be sequentially formed on a substrate. A dielectric layer pattern including metal oxide doped with Group III transition metals may be formed on the floating gate using a pulsed laser deposition process. The dielectric layer pattern having an increased dielectric constant may be formed of metal oxide doped with a transition metal such as scandium, yttrium, or lanthanum.
REFERENCES:
patent: 6642573 (2003-11-01), Halliyal et al.
patent: 2002/0137317 (2002-09-01), Kaushik et al.
patent: 2004/0201058 (2004-10-01), Sonoda et al.
patent: 1998-032692 (1998-07-01), None
patent: 1999-77767 (1999-10-01), None
patent: 2000-23760 (2000-04-01), None
Korean Patent Office Action dated May 18, 2006.
Choi Han-Mei
Choi Jae-Hyoung
Kim Young-Sun
Lee Jong-Cheol
Nam Gab-Jin
Dang Trung
Harness & Dickey & Pierce P.L.C.
Samsung Electronics Co,. Ltd.
LandOfFree
Semiconductor memory device and method of manufacturing the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device and method of manufacturing the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and method of manufacturing the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3967870