Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-07-22
2008-07-22
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S276000, C438S217000, C438S199000, C257SE21689, C257SE21337
Reexamination Certificate
active
11412951
ABSTRACT:
A method of manufacturing a semiconductor device includes forming a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type in a predetermined region of the semiconductor substrate of a first conductive type; and first to third ion implantation processes sequentially executed for controlling threshold voltages corresponding to each transistor formed on the semiconductor substrate the first semiconductor region, and the second semiconductor region respectively. The first ion implantation process is executed in a high-threshold low-voltage transistor forming region of the first semiconductor region after forming the first semiconductor region. The second ion implantation process is executed in a high-threshold low-voltage transistor forming region of the second semiconductor region. The third ion implantation is executed simultaneously in the low-threshold low-voltage transistor forming regions of the semiconductor substrate and the second semiconductor region respectively.
REFERENCES:
patent: 6306709 (2001-10-01), Miyagi et al.
patent: 6677194 (2004-01-01), Yamanaka et al.
patent: 6703670 (2004-03-01), Lines
patent: 6803285 (2004-10-01), Mistry et al.
patent: 7144795 (2006-12-01), Lines
patent: 7161216 (2007-01-01), Lines
patent: 7235476 (2007-06-01), Nakagawa
patent: 2005/0230781 (2005-10-01), Ema et al.
patent: 2006/0091470 (2006-05-01), Noguchi et al.
patent: 2000-323587 (2000-11-01), None
U.S. Appl. No. 11/031,036, filed Jan. 10, 2005, Mitsuhiro Noguchi et al.
U.S. Appl. No. 11/412,951, filed Apr. 28, 2006, Kajimoto et al.
U.S. Appl. No. 11/671,229, filed Feb. 5, 2007, Kato et al.
Kajimoto Minori
Noguchi Mitsuhiro
Ahmadi Mohsen
Geyer Scott B.
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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