Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2008-04-01
2008-04-01
Parekh, Nitin (Department: 2811)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S456000, C438S458000, C438S461000, C257S704000, C257S023000
Reexamination Certificate
active
11201726
ABSTRACT:
As disclosed herein, structures and methods are provided for forming capped chips. As provided by the disclosed method, a metal base pattern is formed on a chip insulated from wiring of the chip, and a cap is formed including a metal. The cap is joined to the metal base pattern on the chip to form the capped chip. In one embodiment, a front surface of the chip is exposed which extends from a contact of the chip to an edge of the chip. In another embodiment, a conductive connection is formed to the contact, the conductive connection extending from the contact to a terminal at an exposed plane above the front surface of the chip.
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Beroz Masud
Haba Belgacem
Tuckerman David B.
Urbish Glenn
Lerner David Littenberg Krumholz & Mentlik LLP
Parekh Nitin
Tessera Inc.
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