Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-10-02
2007-10-02
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S269000, C257SE21104, C257SE21132, C257SE21410
Reexamination Certificate
active
11256424
ABSTRACT:
The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.
REFERENCES:
patent: 4758531 (1988-07-01), Beyer et al.
patent: 5039625 (1991-08-01), Reisman et al.
patent: 5073516 (1991-12-01), Moslehi
patent: 5248385 (1993-09-01), Powell
patent: 5250837 (1993-10-01), Sparks
patent: 5340754 (1994-08-01), Witek et al.
patent: 5753555 (1998-05-01), Hada
patent: 5763305 (1998-06-01), Chao
patent: 6060746 (2000-05-01), Bertin et al.
patent: 6064081 (2000-05-01), Robinson et al.
patent: 6204532 (2001-03-01), Gambino et al.
patent: 6279531 (2001-10-01), Armacost et al.
patent: 6406962 (2002-06-01), Agnello et al.
patent: 6436770 (2002-08-01), Leung et al.
patent: 6437375 (2002-08-01), Beaman
patent: 6448129 (2002-09-01), Cho et al.
patent: 6506638 (2003-01-01), Yu
patent: 6518609 (2003-02-01), Ramesh
patent: 6617226 (2003-09-01), Suguro et al.
patent: 6624032 (2003-09-01), Alavi et al.
patent: 6642539 (2003-11-01), Ramesh et al.
patent: 6703290 (2004-03-01), Boydston et al.
patent: 6713378 (2004-03-01), Drynan
patent: 6716687 (2004-04-01), Wang et al.
patent: 6716719 (2004-04-01), Clampitt et al.
patent: 6746923 (2004-06-01), Skotnicki et al.
patent: 6790713 (2004-09-01), Horch
patent: 6805962 (2004-10-01), Bedell et al.
patent: 6855436 (2005-02-01), Bedell et al.
patent: 6858499 (2005-02-01), Bol
patent: 6878592 (2005-04-01), Besser et al.
patent: 6885069 (2005-04-01), Ohguro
patent: 6946377 (2005-09-01), Chambers
patent: 2001/0010962 (2001-08-01), Chen et al.
patent: 2001/0017392 (2001-08-01), Comfort et al.
patent: 2001/0025985 (2001-10-01), Noble
patent: 2002/0081861 (2002-06-01), Robinson et al.
patent: 2003/0027406 (2003-02-01), Malone
patent: 2003/0153155 (2003-08-01), Wang et al.
patent: 2003/0211712 (2003-11-01), Chen et al.
patent: 2004/0121546 (2004-06-01), Yoo
patent: 2004/0241460 (2004-12-01), Bedell et al.
patent: 2005/0224800 (2005-10-01), Lindert et al.
patent: 2006/0046391 (2006-03-01), Tang et al.
patent: 2006/0051941 (2006-03-01), Biomiley et al.
patent: 2006/0081884 (2006-04-01), Abbott et al.
patent: 2006/0125044 (2006-06-01), Haller
patent: 2006/0264010 (2006-11-01), Ramaswamy et al.
Bashir et al.,Characterization and modeling of sidewall defects in selective epitaxial growth of silicon, J. Vac. Sci. Technol. B, vol. 13, Part 3, pp. 928-935 (May/Jun. 1995).
U.S. Appl. No. 10/932,129, filed Sep. 2004, Ramaswami et al.
U.S. Appl. No. 10/932,151, filed Sep. 2004, Ramaswami et al.
U.S. Appl. No. 11/035,298, filed Jan. 2005, Blomiley et al.
Basceri Cem
Blomiley Eric R.
Ramaswamy Nirmal
Sandhu Gurtej S.
Dang Trung
Micro)n Technology, Inc.
Wells St. John P.S.
LandOfFree
Method of forming a vertical transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a vertical transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a vertical transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3902892