Nonvolatile memory cell comprising a reduced height vertical...

Details Nonvolatile memory cell comprising a reduced height vertical... Nonvolatile memory cell comprising a reduced height vertical...

Filed on

2007-10-23

Date issued

2007-10-23

Examiner

Le, Dung A. (Department: 2818)

Patent Class

Semiconductor device manufacturing: process

SubClass

Making field effect device having pair of active regions...

SubSubClass

Having insulated gate

Other Related Categories

C438S257000, C438S593000, C438S594000, C257S314000, C257S315000

Type

Reexamination Certificate

Status

active

Patent number

11015824

Description

ABSTRACT:
A nonvolatile memory cell according to the present invention comprises a bottom conductor, a semiconductor pillar, and a top conductor. The semiconductor pillar comprises a junction diode, including a bottom heavily doped region, a middle intrinsic or lightly doped region, and a top heavily doped region, wherein the conductivity types of the top and bottom heavily doped region are opposite. The junction diode is vertically oriented and is of reduced height, between about 500 angstroms and about 3500 angstroms. A monolithic three dimensional memory array of such cells can be formed comprising multiple memory levels, the levels monolithically formed above one another.

REFERENCES:
patent: 6034882 (2000-03-01), Johnson et al.
patent: 7026212 (2006-04-01), Herner et al.

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