Skewed inverter delay line for use in measuring critical...

Details Skewed inverter delay line for use in measuring critical... Skewed inverter delay line for use in measuring critical...

2007-08-21

2007-08-21

Lamarre, Guy (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000, C714S700000, C714S709000

Reexamination Certificate

active

11071554

ABSTRACT:
An integrated circuit includes a testable delay path. A transition of a delay path input signal causes a subsequent transition of a delay path output signal. A pulse generator receives the delay path input and output signals and produces a pulse signal having a pulse width indicative of the delay between the delay path input and output signal transitions. A delay line receives the pulse signal from the pulse generator. The delay line generates information indicative of the pulse signal pulse width. The delay line may include multiple stages in series where each stage reduces the pulse width of the pulse signal. The delay line may include a high skew inverter having PMOS and NMOS transistors having significantly different gains. The pulse generator is configured to produce a positive going pulse signal regardless of whether the delay path is inverting or non-inverting.

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Datta, et al., On-Chip Delay Measurement for Silicon Debug; Great Lakes Symposium on VLSI, pp. 145-148, ACM, Apr. 2004.
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Datta, et al., Delay Fault Testing and Silicon Debug Using Scan Chains; European Test Conference, pp. 46-51, IEEE, 2004.

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