Method for manufacturing double-crown capacitors self-aligned to

Details Method for manufacturing double-crown capacitors self-aligned to Method for manufacturing double-crown capacitors self-aligned to

1997-04-11

1998-08-11

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, 438255, H01L 218242

Patent

active

057926891

ABSTRACT:
A method is described using a single photoresist mask to make a double-crown-shaped DRAM capacitor self-aligned to the capacitor node contact. After forming the DRAM FETs and the bit lines, a planar BPSG layer, a first polysilicon layer, and a CVD oxide layer are deposited. A node contact photoresist mask is used to form first openings in the CVD oxide in which silicon nitride sidewall spacers are formed. A smaller second opening is etched in the first opening to form node contact openings to the DRAM FET source/drain areas. A conformal second polysilicon layer is deposited to form node contacts in the second openings and over the free-standing sidewall spacers. A planar spin-on glass layer is then used as a self-aligned mask to etch back to expose the second polysilicon layer, which is then removed from the top of the sidewall spacers. After removing the spin-on glass an anisotropic etch is used to form the double-crown-shaped capacitor bottom electrodes self-aligned to the node contacts. The bottom electrode surface is roughened to increase the capacitance area, and the sidewall spacers are removed. An interelectrode dielectric layer and a third polysilicon layer are used to complete the double-crown-shaped stacked capacitors.

REFERENCES:
patent: 5082797 (1992-01-01), Chen et al.
patent: 5185282 (1993-02-01), Lee et al.
patent: 5281549 (1994-01-01), Fazan et al.
patent: 5554557 (1996-09-01), Koh

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