Techniques for improving negative bias temperature...

Details Techniques for improving negative bias temperature... Techniques for improving negative bias temperature...

2007-08-14

2007-08-14

Jackson, Jerome (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S371000, C257SE21632, C438S475000

Reexamination Certificate

active

11018422

ABSTRACT:
In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.

REFERENCES:
patent: 5229311 (1993-07-01), Lai et al.
patent: 6071784 (2000-06-01), Mehta et al.
patent: 6774462 (2004-08-01), Tanaka et al.
patent: 2003/0183939 (2003-10-01), Kakamu et al.
patent: 2005/0012122 (2005-01-01), Kakamu et al.
patent: 2005/0020021 (2005-01-01), Fujiwara et al.
patent: 2005/0112817 (2005-05-01), Cheng et al.

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