Semiconductor CMOS devices and methods with NMOS high-k...

Details Semiconductor CMOS devices and methods with NMOS high-k... Semiconductor CMOS devices and methods with NMOS high-k...

2007-02-13

2007-02-13

Kebede, Brook (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S204000, C438S200000

Reexamination Certificate

active

11118843

ABSTRACT:
The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.

REFERENCES:
patent: 6528858 (2003-03-01), Yu et al.
patent: 6538278 (2003-03-01), Chau
patent: 6979623 (2005-12-01), Rotondaro et al.
patent: 2002/0151125 (2002-10-01), Kim et al.
U.S. Appl. No. 11/118,237, filed Apr. 29, 2005, Colombo et al.
U.S. Appl. No. 11/118,842, filed Apr. 29, 2005, Visokay et al.

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